Kabushiki Kaisha Toshiba

Toshiba Memory Corporation

Tomoki Higashi

Takashi Ohsawa

Yoshihisa Iwata

Shinichi Oosera

Yasuhiro Shimura

Keisuke Yonehama

Sumito Ohtsuki

Junichi Kijima

Kenji Tsuchida

Hidehiro Shiga

Koki Ueno

Hitoshi Iwai

Yuki Kanamori

Hiroaki Nakano

Ryo Fukuda

Tomonori Kurosawa

Mutsuo Morikado

Mizuki Kaneko

Hiroyuki Noji

Kazumi Tanimoto

Tomohiro Oda

According to one embodiment, a memory controller transmits a first instruction to a memory device. The memory device includes cell transistors; word lines coupled to gates of the cell transistors; a first data latch; and a second latch. The first instruction instructs application of a positive voltage to one of the word lines. The memory controller transmits a second instruction after the transmission of the first instruction and before transmitting a third instruction. The third instruction instructs output of data from the memory device. The second instruction is different from the third instruction and a fourth instruction instructing copy of data from the first data latch to the second data latch.

Memory device and memory controller

According to one embodiment, a semiconductor memory device includes: a memory cell array including a plurality of memory strings, each of the memory strings including a plurality of memory cells connected in series; a plurality of word lines commonly connected to the memory strings and connected to the memory cells; and a control circuit which executes a write operation including a plurality of program loops, each of the program loops including a program operation and a verify operation. When a suspend command for instructing an operation suspend is externally received during execution of the program operation, the control circuit executes a dummy read operation in which the word lines are applied with a voltage after the program operation, and enters into a suspend mode after the dummy read operation.

Semiconductor memory device

A nonvolatile semiconductor memory device comprises a plurality of memory blocks, each including a plurality of cell units and each configured as a unit of execution of an erase operation. Each of the cell units comprises a memory string, a first transistor, a second transistor, and a diode. The first transistor has one end connected to one end of the memory string. The second transistor is provided between the other end of the memory string and a second line. The diode is provided between the other end of the first transistor and a first line. The diode comprises a second semiconductor layer of a first conductivity type and a third semiconductor layer of a second conductivity type.

Nonvolatile semiconductor memory device

According to one embodiment, a resistance-change memory includes bit lines, word lines, a memory cell array including memory cells arranged at intersections between the bit lines and the word lines, each of the memory cells including a variable-resistance element and a diode, a control circuit configured to apply a reverse bias to the diode, and to write data to a selected memory cell, and a current limiting circuit configured to limit a current flowing to the selected memory cell in a write. The current limiting circuit controls the current flowing to the selected memory cell not to exceed a second compliance current obtained by adding a leakage current from an unselected memory cell to a predetermined first compliance current.

Resistance-change memory

A nonvolatile semiconductor memory device according to an embodiment of the present invention includes: a memory cell array having a plurality of memory cells arranged therein, each of the memory cells having a charge storage layer and a control electrode; and a control unit configured to execute a write cycle multiple times, the write cycle including a write operation and a write verify operation, the write operation being an operation for applying a write pulse voltage multiple times to the control electrode selected for data write, and the write verify operation being an operation for determining whether data write is completed or not. During one time of the write operation, the control unit makes a voltage value of a finally applied write pulse voltage larger than a voltage value of an initially applied write pulse voltage.

This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.

Semiconductor storage device and driving method thereof

This disclosure concerns a semiconductor memory device comprising: a memory cell array having memory cells arrayed two-dimensionally; word lines connected to the memory cells of rows of the memory cell array; bit lines connected to the memory cells of columns of the memory cell array; sense amplifiers connected to the bit lines, and detecting data stored in the memory cells; a test pad passing a predetermined reference current from a power source, and transmitting a reference voltage based on the reference current; and test circuits connected between the power source and the test pad and intervening between the power source and the bit lines, the test circuits passing test currents according to the reference voltage via the bit lines.

A memory including; cells, wherein a refresh operation includes a first refresh and a second refresh, in the first refresh, a first potential higher than a gate potential in a retention is applied to the gate in a state having a source potential applied to the drain, and thereafter the gate potential in the retention is applied to the gate, thereby a first current passes to the cell, and in the second refresh, a second potential higher than a gate potential in the retention is applied to the gate, and a third potential higher than the gate potential in the retention is applied to the drain, thereby a second current passes to the cell, and a state of the cell is shifted to an equilibrium state in which amounts of the first and the second currents flowing during one cycle becomes substantially equal.

Semiconductor memory device and driving method thereof

A semiconductor memory including a memory cell which is a MOSFET formed on an SOI substrate. The memory cell has a gate electrode connected to a word line, a drain region connected to a bit line, and a grounded source region. An operation of reading out data written in the memory cell is performed under a biasing condition by which a relationship Vd&#x3e;Vg&#x2212;Vthholds between a gate voltage Vg to be applied to said gate electrode, a drain voltage Vd to be applied to said drain region, a threshold voltage Vthof said MOSFET when a predetermined amount of holes are stored in a body region of the memory cell, and a threshold voltage Vthof said MOSFET when holes whose amount is smaller than the predetermined amount are stored in the body region.

Semiconductor memory and read method of the same

A semiconductor storage device comprises information memory cells into which data can be written or from which data can be read; a memory cell array including the information memory cells arranged in a matrix; information word lines connected to the information memory cells in rows of the memory cell array; information bit lines connected to the information memory cells in columns of the memory cell array; a reference memory cell storing a single kind of digital data to generate a reference potential used to discriminate data stored in the information memory cells; a reference bit line connected to the reference memory cell; and sense amplifiers connected to the information bit lines and the reference bit line.

Semiconductor storage device

A semiconductor storage device includes memory cells having a floating body region and storing data by accumulating or releasing electric charges in or from the floating body region; a memory cell array including a matrix arrangement of the memory cells; a plurality of word lines each connected to the memory cells of each row in the memory cell array; and a counter cell array including counter cells each provided in correspondence to each word line to store occurrences of activation of the word line to read out data from the memory cells.

Semiconductor storage device having a counter cell array to store occurrence of activation of word lines

A semiconductor memory device includes memory cell arrays, word lines, sub-sense lines, main sense line, row decoders, column decoders, first switch elements, read circuit, and write circuit. Each memory cell array has a matrix of memory cells including magnetoresistive elements. Each magnetoresistive element has first and second magnetic layers and a first insulating layer formed between the first and second magnetic layers. The word line is connected to the first magnetic layers on each row. The sub-sense line is connected to the second magnetic layers on each column. The main sense line is connected to each sub-sense line. The row decoder and column decoder select a word line and sub-sense line. The first switch element connects the sub-sense line selected by the column decoder to the main sense line. The read circuit reads out data from a memory cell. The write circuit writes data in a memory cell.

Growing community of inventors

Yokohama, Japan

Tomoki Higashi