Fuji Xerox Co., Ltd.

Tomokazu Kaneko

Kenichi Sonobe

Hirota Takahashi

Hiroshi Sugita

Tsutomu Hoshino

Kazuya Edogawa

Nobukazu Miyoshi

Tsutomu Nakaminato

Asahito Shioyasu

Katsuma Nakamoto

Yoshinobu Terui

Yoshitaka Terui

An information processing apparatus includes a memory that is volatile, a memory controller connected to the memory in an information exchangeable manner, and a clock enable (CKE) controller. The CKE controller controls a CKE signal in response to a request for a proxy in self-refresh control, the CKE signal being transmitted from the memory controller to the memory and being controlled to be kept low until cancellation of the proxy is requested. At a time of shifting to a power-saving mode, the memory controller stores information held by a central processing unit (CPU) in the memory and causes the memory to shift to a self-refresh mode. At a time of recovery from the power-saving mode, the memory controller requests the CKE controller for the cancellation of the proxy in the self-refresh control and thereafter cancels the self-refresh mode of the memory.

Information processing apparatus and information processing method

A data processing apparatus includes: a storage that has first to nstorage areas and stores data in the first to nstorage areas; a specific area erasion section that erases the data stored in the first storage area of the storage; a area erasion section that erases the data stored in at least one of the second to nstorage areas; and a erasion control section that controls the specific area erasion section and the area erasion section so that erasion of the specific area erasion section takes precedence over erasion of the area erasion section, wherein n is natural number.

Data processing apparatus, data processing method, and computer readable medium

While a general-purpose interface circuit and another general-purpose interface circuit are provided so as to transmit/receive data between a host appliance and a device appliance, when the general-purpose interface of the device appliance happens to hang up, a control section transmits a reset signal via a dedicated interface circuit. When a dedicated interface circuit provided on the side of the device appliance receives this reset signal and then outputs this received reset signal to the general-purpose interface circuit, the general-purpose interface circuit is reinitiated.

Device control system

A USB device for performing communications with a second device through a USB interface while supplying electric power to the second device through a power-source supplying line in the USB interface. The USB device includes a communication unit for communicating with the second device, a power source capable of outputting electric power of a voltage being different from a standard power voltage prescribed in the standards of the USB interface. The power source supplies the electric power to the second device through the power-source supplying line. The second device includes a low load unit and a high load unit The power source supplies the electric power having a power voltage higher than the standard power voltage to the high load unit through the power-source supplying line.

USB device that provides power that is different from power prescribed in the USB standard

A USB device for supplying current to a device connected thereto through a USB interface. In this USB device, current values requested by the devices are preset, as detecting current values, in detector registers of current detecting parts. The current detecting parts constantly monitor current values of electric powers supplied to the devices. Each current detecting part compares a related detecting current value with a related supplied current value. If the supplied current value exceeds the detecting current value, the current detecting part informs a current detection control part of abnormality occurrence. The current detection control part sets a bit in a no-good status register, which corresponds to the current detecting part having informed the abnormality occurrence, and interrupts a CPU. In turn, the CPU refers to the no-good status register and specifies the failure device, and interrupts a current supplying path connecting to the failure device.

Detecting device abnormality by comparing a current value of current of electric power with a preset detecting current value based on a threshold value received by the device

In a CPU, a FET is turned off and power is not supplied to a power supply element of a transceiver for a period of time until predetermined initialization processing, which is implemented in a peripheral device when power is supplied via a cable from a host PC, has been concluded (i.e., a period of time until it becomes possible for the peripheral device to initiate data communication with the host PC). Thus, even if the peripheral device and the host PC are physically connected by a cable, data signals transmitted along signal lines are not relayed by the transceiver to a logic controller, whereby it in effect becomes possible to set the peripheral device in a pseudo-non-connected state with respect to the host PC.

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Iwatsuki, Japan

Tomokazu Kaneko