Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Fujitsu Corporation

Tomokazu Higuchi

Tetsuya Hayashi

Masanori Yoshitani

Hideki Takauchi

Hiroshi Shiraishi

A communication test circuit for allowing a tolerance test to be carried out in a general testing environment. The communication test circuit includes an adder and a second clock generation block. When an offset is input to the adder, the adder adds the offset to a phase adjustment signal for adjusting the phase of a clock signal for data detection and outputs the result to the second clock generation block. The second clock generation block outputs a second clock signal adjusted in accordance with the phase adjustment signal to which the offset has been added. Accordingly, a clock signal shifted in accordance with the offset from a natural clock signal along the time axis is generated at a test.

Communication test circuit, communication interface circuit, and communication test method

An electrostatic discharge protection circuit and a semiconductor device that prevent the breakdown of a semiconductor device caused by an electrostatic discharge (ESD) which suddenly changes. When voltage which is far higher than VDDis applied to a power supply line as a result of an ESD, a great electric potential difference is produced between VDDand VSS. At this time an electric current path for making an electric charge generated by overvoltage flow to a grounding line is formed by a clamp circuit. As a result, an electric current flows into GND of a circuit block. This prevents the production of a great electric potential difference between VDDand VSS. In addition, at this time a rapid change in the level of the overvoltage applied to a signal line is suppressed by a protection circuit. This prevents the dielectric breakdown of gate oxide films of transistors included in a circuit block which receives a control signal.

Electrostatic discharge protection circuit and semiconductor device

A signal waveform equalizer circuit capable of equalizing the waveform of an input signal with a center voltage of 0 V and yet small in circuit scale. An input signal (in FIG., positive-phase input signal) whose waveform is to be equalized is input to the source of an nMOS, and this enables the equalizer circuit to handle an input signal with the center voltage 0 V without the need to add an extra circuit. The waveform of the input signal is shaped by a delay circuit including a resistor and a capacitor, and an output signal (in FIG., positive-phase output signal) is output from a node.

Signal waveform equalizer circuit and receiver circuit

A transmission device including: a driver unit which generates an output signal having an amplitude by a resistance division of a power-supply voltage; and an output-amplitude correction unit which generates current according to variation in the power-supply voltage, and corrects the amplitude by using the current.

Transmission device

An output circuit has a data control circuit, a variable resistance circuit, a common-mode voltage detection circuit, an adjusting circuit. The data control circuit controls data included in an output signal according to an input signal, the variable resistance circuit is connected in series with the data control circuit between a first power supply line and a second power supply line. Further, the common-mode voltage detection circuit detects a common-mode voltage of the output signal, and the adjusting circuit adjusts a resistance of the variable resistance circuit according to an output of the common-mode voltage detection circuit. The common-mode voltage of the output signal is adjusted to equal an optional voltage, and an amplitude of the output signal is adjustable.

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Kawasaki, Japan

Tomokazu Higuchi