Hitachi, Ltd.

Hitachi Information Technology Co., Ltd.

Tomoji Nakamura

Kozaburo Kurita

Masato Hamamoto

Kazumi Hatayama

Yuko Ito

Yoshikazu Kiyoshige

Hideki Sakakibara

Michinobu Nakao

Koki Tsutsumida

Hidefumi Yoshida

Masaki Kouno

Takumi Hasegawa

Motoyuki Sato

Nobuo Konami

Jun Matsushima

Yasuyoshi Sunaga

Atsushi Hazeyama

Koichiro Natsume

There is provided a semiconductor integrated circuit in which a ring oscillator is formed by a variable delay circuit to cause the ring oscillator to oscillate (S) at the test operation of the variable delay circuit and it is determined whether the variable delay circuit is normal or abnormal depending on whether the ring oscillator satisfies a predetermined monotonic increase condition (S) and a predetermined linearity condition (S).

Semiconductor integrated circuit

A semiconductor device includes a test target circuit; scan chains that enable scanning of the test target circuit; a first random number generation circuit that forms test patterns supplied to the scan chains; a second random number generation circuit that is provided separately from the first random number generation circuit; and a random number control circuit that uses the random numbers generated by the second random number generation circuit to change the random numbers generated by the first random number generation circuit. In a test of the semiconductor device, since a period of a clock of a scan chain does not need to be longer than that of a clock of a pattern generator, the number of clocks of the pattern generator needed for a test can be prevented from increasing. Accordingly, a test time can be prevented from increasing.

Semiconductor device

A semiconductor integrated circuit test method which reduces the required data volume for testing and efficiently detects faults in a circuit to be tested, the method comprising meansto generate identical pattern sequences repeatedly and meansto control flipped bits in pattern sequences, in order to generate neighborhood pattern sequences and use the neighborhood patterns to test the circuit under test. The neighborhood patterns include, in whole or in part, such pattern sequences as ones without flipped bits, ones with all or some flipped bits in one pattern and ones with all or some flipped bits in consecutive patterns or patterns at regular intervals, the interval being equivalent to a given number of patterns. Because a test pattern generator is provided independently of the circuit to be tested, the problem of a prolonged design period can be eliminated, a loss in the operating speed of the circuit under test is minimized and a high fault coverage can be achieved with less hardware overhead and a smaller volume of test data.

Test method of semiconductor intergrated circuit and test pattern generator

Growing community of inventors

Fussa, Japan

Tomoji Nakamura