Sony Corporation

Micron Technology Incorporated

Sony Semiconductor Solutions Corporation

Tomohito Tsushima

Makoto Kitagawa

Wataru Otsuka

Takafumi Kunihiro

Katsuhisa Aratani

Jun Sumino

Tsunenori Shiimoto

Akira Kouchiyama

Shuichiro Yasuda

Durai Vishak Nirmal Ramaswamy

Nobumichi Okazaki

Hidenari Hachino

Minoru Ishida

Hironobu Mori

Akihiro Maesaka

Chieko Nakashima

Satoshi Sasaki

Wataru Ootsuka

Hajime Nagao

Tsutomu Sagara

Tetsuya Mizuguchi

Masaaki Hara

Hiroaki Narisawa

Hiroshi Yoshihara

Kentaro Ogata

Makoto Kitigawa

Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

Memory devices and memory operational methods

Memory cells, memory systems and methods are described. In one embodiment, a memory cell includes electrodes and a memory element, and a first electrically conductive structure is formed within dielectric material providing the memory element in a low resistance state as a result of a first voltage of a first polarity being applied across the electrodes. Additionally, the first electrically conductive structure is removed from the dielectric material providing the memory element in a high resistance state as a result of a second voltage of a second polarity, which is opposite to the first polarity, being applied across the electrodes. A permanent and irreversible electrically conductive structure is formed within the dielectric material providing the memory element in the low resistance state as a result of a third voltage of the second polarity and having an increased potential compared with the second voltage being applied across the electrodes.

Memory cells, memory systems, and memory programming methods

Memory structures with a plurality of memory cells that each include memory devices in combination with switch devices are provided. The memory device and switch device of each cell are connected in series, and include at least first and second electrodes. The first electrode features a relatively high resistance, to provide a reduced snap current during operation of the memory device. The first electrode with a relatively high resistance can contain or be entirely composed of TiAlN.

Memory cell switch device

Memory systems and memory writing methods

Memory devices and methods of writing memory cells at different moments in time

An integrated circuit system, and a method of manufacture thereof, including: an integrated circuit die; a non-volatile memory cell in the integrated circuit die and having a bit line for reading a data condition state of the non-volatile memory cell; and a voltage clamp in the integrated circuit die, the voltage clamp having a semiconductor switch connected to the bit line for reducing voltage excursions on the bit line.

Integrated circuit system with non-volatile memory stress suppression and method of manufacture thereof

A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled.

Memory device with variable trim parameters

A method of operation of a non-volatile memory system includes: providing a resistive storage element having a high resistance state and a low resistance state; coupling an analog multiplexer to the resistive storage element for applying a bias voltage; and switching between a verification bias and a read bias through the analog multiplexer for increasing a read margin between the high resistance state and the low resistance state.

Non-volatile memory system with reset verification mechanism and method of operation thereof

Memory devices and memory operational methods including single erase operation of conductive bridge memory cells

A method of operation of a non-volatile memory system including: providing a resistive storage element having a transformation layer; activating a write driver, coupled to the resistive storage element, for applying a bias voltage to the transformation layer; monitoring a resistance of the resistive storage element by a sense amplifier; and detecting a conductive thread, formed in the transformation layer, by the sense amplifier for reducing a level of the bias voltage.

Non-volatile memory system with power reduction mechanism and method of operation thereof

Growing community of inventors

Tokyo, Japan

Tomohito Tsushima