Kabushiki Kaisha Toshiba

Tomohito Kawano

Hitoshi Ohta

Akira Umezawa

Hidetoshi Saito

A nonvolatile semiconductor storage device includes a memory cell array including a plurality of memory cells arranged at intersection positions of word lines and bit lines in a matrix form, and a row decoder including a row sub-decoder to which a lower address for selecting a word line is input, wherein one unit of the row sub-decoder for selecting one word line is constituted of a first transistor of a first conduction type, and a second transistor of a second conduction type, and a gate electrode of each of the first and second transistors is arranged in a direction in which the bit lines are arranged.

Nonvolatile semiconductor storage device and method of testing the same

A non-volatile semiconductor memory includes a memory cell array. The memory cell array includes a plurality of banks, redundant blocks, and special blocks storing management data. Each bank includes a plurality of normal blocks, which include a plurality of electrically rewritable memory cells, the normal block being a minimum unit which is independently erased, and the redundant block configured to replace the normal block and being incapable of replacing the special block. A defective block automatic replacement sequence control circuit controls the replacement operation of the defective block FBLK with the redundant block RBLK in a defective block automatic replacement sequence.

Non-volatile semiconductor memory and method for replacing defective blocks thereof

A semiconductor memory device of this invention includes a first bank, a second bank, and a bank decoder that selects a bank to be activated from the first and second banks. When testing operations of first memory cells and second memory cells, the bank decoder simultaneously selects the first and second banks, and first and second write load circuits simultaneously write data in memory cells in first and second blocks, respectively.

Semiconductor memory device to which test data is written

There is disclosed a semiconductor integrated circuit device having first and second load circuits for write. At the time of an all bit-stress test, a high voltage for write is supplied from the first and second load circuits for write to the all bit lines. At the time of an even bit-stress test, the high voltage for write is supplied from the first load circuit for write to the even bit lines and a lower potential than the high voltage for write is supplied from the second load circuit for write to the odd bit lines. At the time of an odd bit-stress test, the lower potential is supplied from the first load circuit for write to the even bit lines and the high voltage for write is supplied from the second load circuit for write to the odd bit lines.

Semiconductor integrated circuit device

A semiconductor memory device includes a data line array connected to a memory cell array, a read circuit configured to charge selected data lines to read data, and a non-selection-side charge circuit configured to charge non-selected data lines. In the data line array, a first group of lower order 8 bit data lines and a second group of higher order 8 bit data lines are alternately disposed one line by one line. The read circuit selects and charges all the 16 bit data lines in a word data read mode, while it selects and charges one of the first and second groups in a byte data read mode. The non-selection-side charge circuit selects and charges non-selected data lines, which belong to the other of the first and second groups not selected by the read circuit in the byte data read mode.

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Yokohama, Japan

Tomohito Kawano