Renesas Electronics Corporation

Tomohisa Sekiguchi

Yuji Kayashima

A wiring is formed over a semiconductor substrate via an interlayer insulation film, and another interlayer insulation film is formed over the interlayer insulation film so as to cover the wiring, and a pad is formed over the another interlayer insulation film. Over the another interlayer insulation film, a layered film having an opening portion in which a pad is exposed is formed, and a redistribution wiring electrically connected to the pad is formed over the layered film and over the pad exposed in the opening portion. An end portion of the wiring is located below a connection region between the pad and the redistribution wiring. The wiring has a plurality of opening portions formed therein, and at least a part of the plurality of opening portions overlaps with the connection region in plan view.

Semiconductor device including first and second wirings

A structure analysis apparatus () for analyzing structure of a complex material layer containing a plurality of members () for modeling layout data on a complex material layer, includes: an area setting portion () for setting an area to be modeled in the complex material layer; an area dividing portion () for dividing the area into a plurality of elements; an area computing portion () for calculating, based on an occupancy of each of the plurality of members () in the area, the number of elements corresponding respectively to the plurality of members (); and an element placing portion () for generating a model of the complex material layer by placing the plurality of members () respectively in the plurality of elements based on the number of the elements corresponding respectively to the plurality of members ().

Method and apparatus for analyzing structure of complex material layer, and storage medium storing program for causing a computer to execute thereof method

Growing community of inventors

Tokyo, Japan

Tomohisa Sekiguchi