Fujitsu Semiconductor Limited

Fujitsu Corporation

Tomohisa Hirayama

Keizo Morita

Naoharu Shinozaki

Shoichiro Kawashima

Toru Endo

Masaki Okuda

A semiconductor memory device includes a memory cell array, a word line decoder, a time determination signal generation circuit, and a timing circuit. The memory cell array is configured to include a plurality of memory cells, and the word line decoder is configured to control selection and a voltage level of a word line connected to each of the memory cells. The time determination signal generation circuit is configured to generate a time determination signal indicating a determination time, the determination time being a reference by which a change in a command is determined, and the timing circuit is configured to determine the change in the command from the time determination signal and generate a control signal which controls whether or not a selected word line is pre-charged.

Ferroelectric memory device and timing circuit to control the boost level of a word line

A ferroelectric memory device includes a memory array including a plurality of ferroelectric memory cells, a code generating circuit configured to multiply write data and a parity generator matrix to generate check bits, thereby producing a Hamming code having information bits and the check bits arranged therein, the information bits being the write data, and a driver circuit configured to write the Hamming code to the memory array, wherein the parity generator matrix has a plurality of rows, and a number of '1's in each of the rows is an even number.

Ferroelectric memory device

A semiconductor memory that includes a memory cell array by which power consumption can be reduced and that enables a reduction in circuit area. In the memory cell array, each of capacitor plate lines is arranged so as to connect with ferroelectric memory cells in a same row, and each of word lines is arranged so as to connect with ferroelectric memory cells in different rows in a column direction. In addition, of drive circuits for driving the capacitor plate lines and the word lines, part of word line drive circuits (WL drive circuits) are arranged in the column direction. Therefore, it is possible to drive all of the word lines without using a dummy area. As a result, circuit area can be reduced.

Semiconductor memory

A bit line is connected, via a first pMOS transistor, to a first node whose potential is set at a prescribed negative voltage in advance. The gate voltage of the first pMOS transistor is set at a constant voltage that is slightly lower than its threshold voltage. During a read operation, a current that flows into the bit line from a memory cell in accordance with a residual dielectric polarization value of a ferroelectric capacitor always leaks to the first node, whereby the potential of the first node increases. The logical value of data stored in the memory cell is judged on the basis of a voltage increase at the first node. Since no control circuit for keeping the potential of the first node at the ground potential during a read operation is necessary, the layout size and the power consumption of a ferroelectric memory can be decreased.

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Kawasaki, Japan

Tomohisa Hirayama