Fujitsu Corporation

Nikon Corporation

Nikon-trimble Co., Ltd

Tomohiro Tanaka

Hiroyuki Kojima

Toshio Yoshida

Yasunobu Akizuki

Koichi Shimizu

Ryuji Kan

Hisashi Yoshida

Itsumi Sugiyama

Masao Ide

Naoko Niimi

Kazuhito Yamada

Soichiro Nakamura

Koki Sugihara

A surveying instrument includes: a survey system; an image sensing system, including first and second image sensing units, the second having an angle of view wider than that of the first; horizontal and vertical angle drivers to rotate the survey and image sensing systems around a surveying instrument vertical and horizontal axes, respectively; a data storage part; an angle detecting part; and a control unit to cause an image, based on image data the first or second generates after imaging, a design data object for showing the design data portion locations included in the image, and coordinate measurement point objects for showing the coordinate measurement points locations, to be surveyed, corresponding to the design data portion included in the image, to appear on a representation device in response to the design data stored in the data storage part and the detected angle.

Surveying instrument and program

A storage device includes: a first disabling unit configured to output write enable signals without change when at least two write addresses of a plurality of write addresses for which write enable signals are enabled and held by a first holding unit do not match; a second holding unit configured to hold sets of the plurality of write addresses held by the first holding unit and the plurality of write enable signals output by the first disabling unit; a second disabling unit configured to output one write enable signal of the plurality of write enable signals held by the second holding unit without change in a test mode; and a third holding unit configured to write data in accordance with sets of the plurality of write addresses held by the second holding unit and the plurality of write addresses output by the second disabling unit.

Multi-port register file device and method of operation in normal mode and test mode

A memory circuit includes, a latch circuit that includes a first node, a second node, a first inverter having an input coupled to the first node and an output coupled to the second node, and a second inverter having an input coupled to the second node and an output coupled to the first node, a writing circuit that includes a first transistor coupled to the first node and a second transistor coupled to the second node and executes writing to the latch circuit using the first transistor and the second transistor, a command circuit detects the execution of the writing to the latch circuit and output a command signal to increase the potential of the second node before the termination of the writing of a low level to the first node, and a potential control circuit increases the potential of the second node based on the command signal.

Memory circuit and control method for memory circuit

A magnetic body simulation device includes a memory; and a processor coupled to the memory and the processor configured to decide a search section for searching a rotational coefficient of each magnetization vector in a plurality of elements included in a magnetic body, in a process of calculating the each rotational coefficient in a state in which magnetic energy of the magnetic body is minimized, to determine whether or not a first condition is satisfied in which a width of the decided search section is less than or equal to a certain length, and a first rotational coefficient decided by a predetermined method is included in the search section, and to calculate, when the first condition is satisfied, a static magnetic field vector corresponding to the first rotational coefficient by linear interpolation based on static magnetic field vectors at both ends of the search section.

Magnetic body simulation device, micro-magnetization calculation method, and non-transitory computer-readable recording medium having stored therein a program

A register file device includes: a multi-port latch; and a write circuit that generates a signal to be written in the multi-port latch, the write circuit generating the signal on the basis of a plurality of data groups each including a write control signal, a write address, and a piece of write data, wherein the write circuit includes: a detection circuit that detects at least two write control signals occurred simultaneously among write control signals, and a changing circuit that changes write data corresponding to one of the write control signal to become same as write data corresponding to another of the write control signal.

Register file device

A selector circuit includes a plurality of first selection circuits each configured to select one of plural input signals on the basis of a first selection control signal and to output a first output signal and a second selection circuit configured to select one of the first output signals on the basis of a second selection control signal. Each of the first selection circuits includes a charging circuit configured to charge a first node by electrically connecting the first node to a first voltage in a first period, and a discharge control circuit configured to control, on the basis of the first selection control signal, the input signals and the second selection control signal, whether to discharge the charged first node by electrically connecting the first node to a second voltage source having a potential lower than the first voltage source in a second period following the first period.

Selector circuit and processor system

In a scanning-capable latch circuit, main latch circuits respectively corresponding to data inputs Dto Dare connected in series and, except the last-stage main latch circuit, the scanning output from each main latch circuit becomes the scanning input for the subsequent main latch circuit; while the scanning output from the last-stage main latch circuit becomes the scanning input for a slave latch circuit. Hence, in the scanning-capable latch circuit used in an information processing apparatus, the circuit area can be reduced and scanning can be performed with a small-scale circuit.

Scanning-capable latch device, scan chain device, and scanning method with latch circuits

An integrated circuit power consumption calculating apparatus obtains power consumption of an integrated circuit by outputting circuit component transistor connection information of each of circuit components after setting a group of transistors connected via a source terminal/drain terminal of a transistor within each cell of an integrated circuit, by outputting circuit component logic model information after extracting a logic for each of the circuit components from the circuit component transistor connection information information, by obtaining power information (circuit component power information) of each signal transition state of an input/output terminal for each of the circuit components based on the circuit component transistor connection information information, by generating signal terminal transition information with a logic simulation performed for each of the circuit components of the integrated circuit, and by obtaining power consumption in a signal transition of an input/output terminal of each of the circuit components.

Integrated circuit power consumption calculating apparatus and processing method

A disclosed memory circuit includes first and second latch circuits, each writing a write data at a timing of a clock signal and retaining the write data, the write data having been input in each of the first and second latch circuits, a data input circuit supplying the write data to each of the first and second latch circuits when a write enable signal indicates a state allowing the write data to be written, a write back circuit supplying the write data retained in the second latch circuit to the first latch circuit when the write enable signal indicates a state preventing the write data from being written, wherein a robustness against noise in the second latch circuit is more improved than that in the first latch circuit.

Memory circuit and method of writing data to and reading data from memory circuit

An instruction execution control device operates a plurality of threads in a simultaneous multi-thread system. The device has architecture registers (--) for each thread, and a selection circuit () which, when an operand data required for executing a function is read from a register file (), selects in advance a thread to be read from the register file (). This makes it possible to select an architecture register at an early stage, and although the number of circuits in a portion for selecting the architecture registers increases, the wiring amount of the circuits can be decreased, because the architecture register of the thread to be read is selected in advance.

Instruction execution control device and instruction execution control method

A register file device has a memory array, a scan connection configuration circuit, a file writing unit, a file reading unit, and a scan control circuit. The memory includes first storage devices which are obtained by adding shift transfer gate and an output gate to a master flip-flop only latch in a conventional register file using master flip-flop only latch storage devices, and a scan connection configuration circuit and a scan control circuit using master flip-flop only second storage devices are added thereto to realize the scan function of internally constituting a shift register and reading contents thereof in testing. The size of the register file is reduced by using master flip-flop only latch storage devices, and a high test/diagnosis efficiency is achieved by using the internal scan function in master-slave type flip-flop (2 latches) storage devices.

Register file and its storage device

An operation signal generator circuits are provided to continue to operate an object circuit which is not operated unless an operation signal arrives for the purpose of power consumption reduction, and thereby the object circuit is put into dummy operation. This enables an influence of environmental factors, which may affect operation of the circuit element included in the object circuit, to be maintained in a stable or balanced state, and also enables stable and accurate operation of the object circuit at the time of actual operation, with reduced power consumption.

Method for stabilizing electronic circuit operation and electronic apparatus using the same

A plurality of conduction control circuits controls conduction of input signals. A logical operation circuit receives output signals from each of the conduction control circuits via a plurality of signal paths, and performs a logical operation on each of the output signals to output a single signal. A signal-level setting circuit sets, when the conduction of the input signals in the conduction control circuits connected to a same signal path is blocked, a signal level of the signal path. A control-signal generating circuit generates a first control signal that controls the conduction control circuits to select only one input signal for conduction, and a second control signal that controls the signal-level setting circuit to set the signal level of the signal path, by performing a logical operation on a same input signal.

Selector circuit

A lightwave distance measuring apparatus having a coaxial light-transmitting/receiving type optical system is provided with light-transmitting means for transmitting pulsed light toward an object, light-receiving means for receiving reflected pulsed light reflected by the object, a time measuring section for measuring a period of time from when the pulsed light is transmitted until the light is received, a distance measuring section for determining a distance to the object from the measured period of time, and a pulse number detecting section for detecting whether the number of received pulses of reflected light in response to one transmitting pulsed light is one or more; while the value measured when only one pulse of the reflected light is detected by the pulse number detecting section in response to the transmission of pulsed light is made effective.

Growing community of inventors

Kawasaki, Japan

Tomohiro Tanaka