Seiko Instruments Inc

Other

Ablic Inc.

Sii Semiconductor Corporation

Tomohiro Oka

Fumiyasu Utsunomiya

Minoru Ariyama

Yutaka Satou

Teruo Suzuki

Kotaro Watanabe

Yoshihide Kanakubo

Takeshi Naka

Masaya Murata

Naohiro Hiraoka

Ayaka Otani

Yusuke Ezawa

A zero cross detection circuit has a first comparator circuit receiving a first input signal and a second input signal and outputting a first comparison result, a second comparator circuit having a hysteresis function, receiving the first input signal and the second input signal, and outputting a second comparison result, a power supply voltage detection circuit outputting a detection signal when a power supply voltage to be supplied becomes equal to or larger than a predetermined voltage, and a logic circuit outputting a zero cross detection signal based on the first comparison result, the second comparison result, and the detection signal.

Zero cross detection circuit and sensor device

To provide a switch circuit which is capable of reliably controlling transmission of a voltage from GND to VDD to an internal circuit or shut-off thereof even when a positive or negative voltage is inputted to an input terminal, and thereby reduces the risk of latch-up. A switch circuit is comprised of NMOS transistors, and the gates of the NMOS transistors are controlled by an output voltage of a boosting circuit, thereby making it possible to reliably control transmission or shut-off of a voltage from GND to VDD.

Switch circuit

Provided is a semiconductor device including a test mode circuit capable of changing the semiconductor device into a test mode with fewer malfunctions and without providing a test terminal. The semiconductor device includes a test circuit configured to compare data of a data input terminal and a data output terminal in synchronization with clock, and control whether or not to change the semiconductor device into a test mode in accordance with a result of the comparison.

Semiconductor device

A boosting circuit is provided which performs an appropriate boosting operation in accordance with load capacitance. In the boosting circuit, a slope control circuit is provided between a limiter circuit, which limits a high voltage obtained by a charge pump circuit to a desired boosted voltage VPP, and a discharge circuit, which makes the boosted voltage VPP drop quickly to a power supply voltage VCC after the completion of writing, to enable a boosting operation in an appropriate boosted-voltage reach time, by increasing the time taken to reach the boosted voltage VPP in the case where the load capacitance is low, while keeping the time taken to reach the boosted voltage VPP unchanged, irrespective of the presence/absence of the slope control circuit, in the case where the load capacitance is high as in the case of selecting the memory cells collectively.

Boosting circuit

The power-on reset circuit includes: a NMOS transistor having a source connected to a second power supply terminal and a gate connected to a drain thereof; a depletion-type NMOS transistor having a source connected to the drain of the NMOS transistor, a drain connected to a first power supply terminal and a gate connected to the second power supply terminal; a PMOS transistor having a source connected to the first power supply terminal, a gate connected to the drain of the NMOS transistor and a drain; a capacitor having one end connected to the drain of the PMOS transistor and the other end connected to the second power supply terminal; and a waveform shaping circuit having an input terminal connected to the drain of the PMOS transistor and an output terminal from which a power-on reset signal is output.

Power-on reset circuit

Provided is a boosting circuit which avoids a malfunction of a peripheral circuit to be connected to the boosting circuit. The boosting circuit includes: a first discharge circuit for discharging a voltage of a first output terminal when a boosting unit stops a boosting operation; and a second discharge circuit for discharging a voltage of a second output terminal. The second discharge circuit discharges the voltage of the second output terminal to a potential of the first output terminal when a difference voltage between the voltage of the second output terminal and the voltage of the first output terminal is equal to or lower than a predetermined voltage.

Provided are a memory circuit having a small circuit scale and a voltage detection circuit including the memory circuit. An NMOS transistor () is in an off state during loading and writing and is in an on state during reading. An NMOS transistor () is turned on when a high level input is received and turned off when a low level input is received. An NMOS transistor () is in the off state during loading and writing and is in the on state during reading. A PMOS transistor () is in the on state during loading and is in the off state during writing and reading. A PMOS transistor () is turned off when the high level input is received during loading, is turned on when the low level input is received during loading, and is in the on state during writing and reading.

Memory circuit and voltage detection circuit including the same

A voltage switching circuit selects a voltage from among a plurality of input voltages in response to a selection signal and outputs the selected voltage from an output terminal. The voltage switching circuit includes a first PMOS transistor that outputs a power supply voltage for operating a logic circuit of an output terminal. A second PMOS transistor outputs a first voltage higher than the power supply voltage to the output terminal. A third PMOS transistor outputs a second voltage lower than the power supply voltage to the output terminal. A well potential control section controls well voltages of the first and third transistors to be the power supply voltage where the power supply voltage and the second voltage are output to the output terminal, and controls the well voltages of the first and third transistors to be the first voltage where the first voltage is output to the output terminal.

Voltage switching circuit

Provided is a semiconductor memory device, which realizes characteristic evaluation even in a case where a threshold voltage is a negative potential by a test method which is similar to a case of a positive potential. The semiconductor memory device includes a plurality of memory cells for storing data. When a test signal is input, the semiconductor memory device changes from a normal mode to a test mode for evaluating characteristics of the plurality of memory cells. The semiconductor memory device also includes: a memory cell selecting portion for selecting a memory cell; a constant voltage portion for generating a reference voltage; a constant current portion for generating a reference current; an X switch voltage switching control circuit for supplying one of an X selection signal and a voltage signal input from an external terminal to a gate of the memory cell; a Y switch portion for supplying the reference current to a drain of the memory cell selected by a Y selection signal; a comparator for detecting whether or not a drain voltage that is a voltage of the drain has exceeded the reference voltage; and a decision level changing portion for adjusting a current value of the reference current and a voltage value of the reference voltage so as to change a decision level of the comparator based on a control signal in the test mode.

Semiconductor memory device

A boosting and step-down switching regulator includes one error amplifying circuit, and an output of the error amplifying circuit is compared with a triangular wave for boosting and a triangular wave for step-down different in voltage level from each other but synchronous with each other in comparison circuits, respectively, to switch the boosting operation and the step-down operation over to each other. Thus, the boosting operation and the step-down operation can be readily switched over to each other irrespective of an input voltage and an output voltage.

Growing community of inventors

Chiba, Japan

Tomohiro Oka