Fujitsu Corporation

Tomohiro Nakayama

Masakazu Kimura

Yutaka Fukutani

Hiroyuki Fujimoto

Yoshitaka Takahashi

Waichiro Fujieda

Masanori Nagasawa

Atsushi Fujii

Tutomu Taniguti

Seizi Hirayama

Arayama Youji

Takanori Shiga

Kouji Ueno

Yoshiyuki Fujita

Nobuo Ikuta

Kouji Shishido

Youji Arayama

A nonvolatile semiconductor memory is provided with a main memory array and a sub-memory array. When rewriting a portion of data having been written in the main memory cell array, a modification data is written into the sub-memory cell array without erasing said main memory cell array. Further, correspondent information on a first address of the main memory cell array storing a data to be modified and a second address of the sub-memory cell array storing the modification data is recorded. At the time of a readout operation, a readout address is compared with the first address recorded in the correspondent information. When said comparison result indicates consistency, a data in the sub-memory cell array of the second address corresponding to the first address is read out. Otherwise, when the comparison result indicates inconsistency, a data in the main memory cell array corresponding to the readout address is read out.

Nonvolatile semiconductor memory having partial data rewriting function

Memory cell blocks to are respectively provided with mask ROM cell rows and different values from one another are respectively stored in the mask ROM cell rows. A mask ROM cell row selecting circuit makes transfer gates of mask ROM cells in a memory cell block corresponding to a block selection signal BSi turned on when a test mode signal *TM and the block selection signal BSi are both active wherein i&equals;1 to 7. A word line selection signal is made inactive when the test mode signal *TM is active. Tests on short between address signal lines and other defects are effected in a procedure wherein a test mode is activated, block selection signals are sequentially activated to read contents of mask ROM cell rows and the contents are compared with expected values.

Flash memory device having mask ROM cells for self-test

A semiconductor memory device is provided with terminals for receiving a chip enable signal and an address signal, an internal circuit, and an internal control signal generating circuit for generating a predetermined internal control signal which makes an output timing of the semiconductor memory device same regardless of a level of the address signal when the chip enable signal undergoes a transition from an inactive level to an active level. The internal circuit is deactivated in response to the inactive level of the chip enable signal and is activated in response to the active level of the chip enable signal.

Programmable semiconductor memory device

A semiconductor integrated circuit device with a copy-preventive function comprises a memory for storing data to be used by users, an input unit for performing various logical operations on at least one input information fed externally and accessing the memory, an output unit for performing various logical operations on the data at the time of supplying the data from the memory, a judging unit for comparing at least one of the state of the input information, the logical state of the input unit, the logical state of the output unit, and the state of data provided by the output unit with specific judgment information and indicating the result of comparison, and a control unit that when the result indicated by the judging unit reveals that the at least one of the states is consistent with a specific state, acts at least on the output unit so as to prevent data stored in the memory from being supplied normally. Due to this configuration, a copy-preventive function can be reformed frequently from both the aspects of software and hardware. Consequently, illegal copying of data can be substantially disabled.

Semiconductor integrated circuit device with copy-preventive function

An object of the present invention is to improve the output speed of a data signal output circuit having a latch circuit when the supply voltage is low. The data signal output circuit according to the present invention includes a latch circuit; an output circuit; a latch control circuit; an output control circuit; and a supply voltage decrease detection circuit. The latch circuit latches and holds a data signal according to a latch signal output from the latch control circuit. By setting the latch signal to one of two logical states, the latch circuit changes to a through state directly outputting an input data signal. The output circuit changes between a state for outputting a data signal from the latch circuit and a high-impedance state according to an output control signal output from the output control circuit. The supply voltage decrease detection circuit detects whether or not the supply voltage is less than a pre-determined value. When the supply voltage decrease detection circuit detects that the supply voltage is less than the pre-determined value the latch control circuit outputs a latch signal to set the latch circuit to the through state and the output control circuit outputs an output control signal to set the output circuit to output the data signal from the latch circuit.

Data signal output circuit and semiconductor memory device including the

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Kawasaki, Japan

Tomohiro Nakayama