Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Tomohiro Kurozumi

Osamu Ichikawa

Hironori Akamatsu

Masashi Agata

Seiji Yamaguchi

Yasuhiro Agata

Katsuji Satomi

Toru Kakiage

Koutarou Hirai

Shiro Yoshioka

Shintaro Nagai

In a semiconductor memory device, a non-volatile element sectionstores information necessary for rescuing a main memory cell, as storage information, in a non-volatile element. When rescue information Sis newly outputted by a redundancy rescue section, a rescue determination sectiondetermines whether or not a main memory cell is to be rescued, based on storage information Sstored in the non-volatile element section, and the rescue information Swhich is newly outputted. The non-volatile element sectionrenews the storage information based on a determination result from the rescue determination section. Thus, on the assumption that power is turned off each time a voltage condition is changed, the semiconductor memory deviceis capable of determining whether or not the rescue is to be performed, based on results of testings performed under a plurality of voltage conditions.

Semiconductor memory device

In a semiconductor device having a redundant memory, the area of the device is reduced and a time required to transfer relief information is reduced. Moreover, a transfer control of relief information is facilitated. A first relief information storing unit stores relief information for relieving a redundant memory having a defective cell. A plurality of redundant memories share a second relief information storing unit. The second relief information storing unit is connected in series to the first relief information storing unit. The relief information is transferred from the first relief information storing unit to the second relief information storing unit.

Semiconductor device

Each of a plurality of redundant memories includes a plurality of memory cells and is operable to be relieved when a defective cell exists. This plurality of redundant memories can operate independently of each other. A relief processing portion is shared by this plurality of redundant memories. A test circuit inspects the plurality of redundant memories. When the test circuit determines that a defective cell exists, the test circuit outputs relief information to relieve the defective cell. The relief processing portion has a plurality of defect relief portions each having a relief information storage portion operable to store the relief information and performs the processing of relieving the plurality of redundant memories.

Semiconductor device with a relief processing portion

A relief processing section which performs a relief process with respect to a redundant memory comprises a plurality of defect relief sections each having shift register circuits (relief information storing section). The shift register circuits are connected in series so as to successively transfer data. A test circuit tests the redundant memory, and serially outputs relief information for relieving a defective cell. The relief processing section stores the relief information into the shift register circuits using a data transfer operation thereof.

Redundant memory incorporating serially-connected relief information storage

A control system for controlling a cache tag memory has an address conversion device which includes an associative storage for storing logical addresses, a random access memory for storing physical addresses, and a hit-signal generating circuit for generating a hit signal, a word selecting signal and at least one control signal. The hit signal indicates that a hit has occurred between a logical address stored in the associative storage and an input logical address. The address conversion device controls the reading operation of a tag address stored in the cache tag memory by using the control signal generated by the hit-signal generating circuit in synchronization with a word selecting signal used in the reading operation of a physical address stored in the random access memory such that the physical address and the tag address are read at substantially the same time. Further, this address conversion device controls a reading operation of the data stored in the cache memory by reading the physical address and the tag address at substantially the same time and by using a second control signal generated by the hit-signal generating circuit in synchronization with the word selecting signal. Moreover, the address conversion device controls the reading of data from the cache memory and the production of a cache hit signal, which is generated when the physical address matches the logical address. Accordingly, a high-performance system is achieved.

Control systems having an address conversion device for controlling a

An AND circuit having a first input terminal, a second input terminal and an output terminal, and is defined by a P-channel MOS FET, an N-channel MOS FET, a NPN bipolar transistor and a resistor. The P-channel MOS FET has a source connected to the first input terminal and a gate connected to the second input terminal. The N-channel MOS FET has a gate connected to the second input terminal, a source connected to the ground and a drain connected to the drain of the P-channel MOS FET. The transistor has a base connected to the drain of the P-channel MOS FET, and the collector-emitter thereof connected between an electric power supply line and the ground. The resistor is connected in series to the collector-emitter of the transistor. One end of the resistor is connected to the output terminal. The AND circuit has less MOS FETs so that the layout area can be reduced.

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Kyoto, Japan

Tomohiro Kurozumi