Kioxia Corporation

Toshiba Memory Corporation

Tomohiro Kuki

Tatsufumi Hamada

Shinichi Sotome

Yosuke Mitsuno

Yasuhiro Uchimura

Yasuhiro Shimura

Ryota Suzuki

Yuya Akeboshi

Yasunori Oshima

Muneyuki Tsuda

Yusuke Morikawa

Yosuke Mutsuno

Osamu Arisumi

In one embodiment, a method of manufacturing a semiconductor device includes forming a stacked film alternately including first layers and second layers in a first direction, forming a hole extending in the first direction in the stacked film, and forming a first insulator on a side face of the stacked film in the hole. The method further includes removing the first insulator in the hole to expose a first part of the side face of the stacked film at a predetermined height in the first direction of the hole and to expose a side face of the first insulator remaining on a second part of the side face of the stacked film at the predetermined height. The method further includes forming a second insulator on the first part of the side face of the stacked film and the side face of the remaining first insulator in the hole.

Three-dimensional type NAND memory device

According to one embodiment, a semiconductor storage device includes a substrate, a first electric charge holder, and a channel layer. At least a part of the first electric charge holder is curved in a first cross section along a surface of the substrate. The channel layer is inside the first electric charge holder in the first cross section. At least a part of the channel layer is curved in the first cross section. The first electric charge holder has a curvature varying in accordance with a position in the first cross section. The channel layer has a film thickness varying in accordance with the curvature of the first electric charge holder in the first cross section.

Semiconductor storage device and method of manufacturing semiconductor storage device

A semiconductor storage device includes a first stacked body, a second stacked body, an intermediate insulating layer, and a plurality of columnar bodies. The intermediate insulating layer is located between a first stacked body and a second stacked body and has a thickness in the stacking direction larger than that of one insulating layer in the plurality of insulating layers of the first stacked body. The plurality of columnar bodies are provided over the first stacked body and the second stacked body, and each columnar body includes a semiconductor body, a charge storage film provided between at least one of the plurality of conductive layers and the semiconductor body, and a semiconductor film. Each of the plurality of columnar bodies include a first columnar portion formed in the first stacked body, a second columnar portion formed in the intermediate insulating layer, and a third columnar portion formed in the second stacked body. A width of the semiconductor film in the second columnar portion in a direction intersecting the stacking direction is the shortest at an upper end of the intermediate columnar portion and the longest at a lower end of the intermediate columnar portion.

Semiconductor storage device and method for manufacturing semiconductor storage device

A semiconductor device includes: a first stacked film including first electrode layers; an insulating layer provided on the first stacked film; a second stacked film provided on the insulating layer and including second electrode layers; and a columnar portion extending through the first stacked film, the insulating layer, and the second stacked film. The columnar portion extending in the insulating layer includes a first portion having a first width in a second direction intersecting the first direction, and a second portion provided at a different location along the first direction and having a second width in the second direction. The columnar portion extending in the second stacked film includes a third portion having a third width along the second direction. The second width is larger than the first width and the third width.

Semiconductor device and method for manufacturing the same

According to one embodiment, a memory device includes a substrate; a structure including a plurality of conductive layers stacked on the substrate; and a pillar arranged inside the structure and including a semiconductor layer that extends in a direction perpendicular to a surface of the substrate. The semiconductor layer includes a first portion on a side of an upper portion of the structure, and a second portion between the first portion and the substrate. The first portion has a thickness larger than a thickness of the second portion.

Memory device

A semiconductor storage device includes: conductive layers arranged in a first direction; a first insulating layer extending in the first direction; a first semiconductor layer between the conductive layers and the first insulating layer; and a gate insulating film between the conductive layers and the first semiconductor layer. The first semiconductor layer includes a first region between a first insulating portion and the first conductive layer, a second region between a second insulating portion and the second conductive layer, and a third region between the first region and the second region. The third region includes a fourth region extending in a second direction, a fifth region between the first region and the fourth region, a sixth region between the second region and the fourth region, and a seventh region between the fifth region and the first region and extending in the first direction.

Semiconductor storage device and manufacturing method thereof

According to one embodiment, a semiconductor memory device includes: a substrate; a semiconductor above the substrate functioning as a channel of a cell transistor; a first silicon nitride layer above the semiconductor having an internal compressive stress of a first value; and a second silicon nitride layer above the first silicon nitride layer having an internal compressive stress of a second value. The second value is greater than the first value.

Semiconductor memory device

According to one embodiment, a semiconductor memory device includes a stacked body of first conductor layers and second conductor layers. A pillar including a semiconductor layer extends along through the stacked body in a first direction. A charge storage layer is between the conductor layers and the semiconductor layer. The semiconductor layer includes a first portion extending along the first direction from an uppermost first conductor layer to a lowermost second conductor layer and a second portion above the first portion in the first direction. The second portion has a diameter that decreases with increasing distance along the first direction from the first portion.

Semiconductor memory device and manufacturing method of semiconductor memory device

According to one embodiment, a semiconductor memory device includes a base layer, conductive layers, an insulation layer, a semiconductor layer and a charge storage layer. The conductive layers are stacked above the base layer in a first direction. The insulation layer is extending in the conductive layers in the first direction. The semiconductor layer is arranged between the insulation layer and the conductive layers. The charge storage layer is arranged between the semiconductor layer and the conductive layers. The insulation layer includes a first insulation layer arranged on a side of the base layer and containing polysilazane and a second insulation layer arranged on the first insulation layer on a side opposite from the base layer.

A storage device includes bit lines including a first bit line and a second bit line, memory units including a first memory string having memory cells connected in series, connected to the first bit line, and a second memory string having memory cells connected in series, connected to the second bit line, word lines each connected in common to a gate of a memory cell in the first string and a gate of a memory cell in the second string, and a controller configured to control voltages applied to the bit lines and the word lines during writing. When writing is performed on a selected memory cell of the first memory string, a first voltage is applied to a selected word line connected to the gate of the selected memory cell while a second voltage higher than a zero voltage is applied to the first bit line.

Growing community of inventors

Yokkaichi Mie, Japan

Tomohiro Kuki