Elpida Memory, Inc.

Ps4 Luxco S.a.r.l.

Other

Tomohiro Kitano

Hisayuki Nagamine

Disclosed herein is a device that includes: first and second memory cell arrays arranged in a first direction; a plurality of first bump electrodes disposed between the first and second memory cell arrays and arranged in line in a second direction crossing the first direction; a plurality of second bump electrodes disposed between the first bump electrodes and the second memory cell arrays and arranged in line in the second direction; a first area being between the first and second bump electrodes; a plurality of third bump electrodes disposed in the first area; and a first capacitor formed in the third area.

Semiconductor device having compensation capacitor to stabilize power supply voltage

A semiconductor device comprises a first external terminal having a first size, a plurality of second external terminals each having a second size smaller than the first size, an external terminal area in which the first external terminal and the second external terminals are arranged, and a plurality of wires connecting between the second external terminals and a plurality of circuits formed adjacent to the external terminal area and corresponding to the second external terminals. The second external terminals and the wires constitute a plurality of interfaces. Each of the interfaces includes at least one adjustment portion that adjusts a time constant of the wire so that the wires have the same time constant. At least part of the adjustment portions is located in a margin area produced in the external terminal area by a difference between the first size and the second size.

Semiconductor device

A design method for a semiconductor integrated circuit includes a first step (S) of grouping pins that configure a same net into a plurality of groups; a second step (S) of defining sub-trunk wirings mutually connecting the pins that belong to a same group; a third step (S) of defining a main trunk wiring substantially parallel to the sub-trunk wirings; and a fourth step (S) of defining a lead-in wiring connecting at least the main trunk wiring and the sub-trunk wirings. Thus, a plurality of pins are grouped, and the groups are mutually connected by the sub-trunk wirings, making it possible to decrease the number of the lead-in wirings. Thereby, even when the number of nets is large relative to the area of a layout region, a probability of occurrence of nets where automatic wiring is impossible can be greatly reduced.

Method and apparatus for semiconductor integrated circuit

A design method of a semiconductor device is provided with a mask region setting step of setting a mask region to a layout of the semiconductor device, a parasitic parameter changing step of setting parasitic parameters of a wiring part within the mask region to zero, and a parasitic parameter extraction step of extracting parasitic parameters of either the total layout or a specific part of the layout. The parasitic parameter changing step includes a virtual wiring layer generation step of generating a virtual wiring layer corresponding to the actual wiring layer of the semiconductor device, a parasitic parameter definition step of defining the parasitic parameters of the virtual wiring layer as zero, and a wiring layer conversion step of converting the wiring part within the mask region of the wiring of the actual wiring layer, to the wiring part of the virtual wiring layer.

Semiconductor device design method, semiconductor device design system, and computer program for extracting parasitic parameters

The relative placement orders of cells with respect to circuit diagram information received are automatically determined, and the cells are automatically placed in relative positional relationships according to the placement orders given to the circuit diagram information.

Design method, design apparatus, and computer program for semiconductor integrated circuit

A standard cell is split into a plurality of regions, and shareability information having pin information is added to a cell library for each of the split regions. Through comparison of shareability information, a determination is made as to whether, at the time of automatic placement, a standard cell can be placed so as to share part of its region with a standard cell placed adjacent to that standard cell. On the basis of the determination result, when placing a standard cell, a standard cell to be placed adjacent to that standard cell is placed so as to share part of its region, thereby making it possible to reduce the placement area.

Growing community of inventors

Tokyo, Japan

Tomohiro Kitano