Fujitsu Semiconductor Limited

Fujitsu Corporation

Fujitsu Microelectronics Limited

Tomohiro Kawakubo

Shinya Fujioka

Koichi Nishimura

Kotoku Sato

Hitoshi Ikeda

Tatsuya Kanda

Hiroyuki Kobayashi

Toshiya Uchida

Tatsushi Otsuka

Ayako Sato

Shinnosuke Kamata

Hidenaga Takahashi

Tetsuo Miyamoto

Yoshinobu Yamamoto

Masanori Kurita

Satoru Shirakawa

Syusaku Yamaguchi

Hiroyoshi Tomita

Atsushi Takeuchi

Toshikazu Nakamura

Takahiko Sato

Toru Koga

Yoshiaki Okuyama

Shinya Fujijoka

A semiconductor memory has a memory cell array having a plurality of real word lines, a plurality of redundant word lines, a plurality of bit lines crossing with the real and redundant word lines, a plurality of memory cells provided at crossing section of the real and redundant word lines and the bit lines, and a row selection circuit for selecting the real word line or the redundant word line in accordance with a row address being supplied. The row selection circuit selects the real word line or the redundant word line at an ordinary operation, and multi-selects the redundant word lines at a first test mode.

Semiconductor memory with redundant word lines, system, and method of manufacturing semiconductor memory

A semiconductor device includes a memory core with a plurality of memory cells, an internal voltage generator and a low power entry circuit. The low power entry circuit receives a plurality of control signals which are provided to a command decoder, and generates a low power signal indicating a low power consumption mode where a refresh operation is prohibited. The internal voltage generator includes a detector and at least one of booster circuits. The internal voltage generator, coupled to the memory core via an internal power supply line, generates a boosted internal voltage based on an external voltage and supplies the boosted internal voltage to the memory core via the internal power supply line. The internal voltage generator stops supplying the boosted internal voltage to the internal power supply line in response to the low power signal while the external voltage is supplied to the semiconductor device.

Semiconductor memory device and method of controlling the same

Operation control circuits start a first operation of any of memory cores in response to a first operation command, start a second operation of any of the memory cores in response to a second operation command, and terminate the first operation and continue the second operation in response to a termination command to terminate operations of the plurality of memory cores. For example, the semiconductor memory is mounted on a system together with a controller accessing the semiconductor memory. The termination of the operation in response to the termination command is judged in accordance with an operation state of the memory core. Accordingly, it is possible to terminate the operation of the memory core requiring the termination of operation without specifying the memory core from outside.

Semiconductor memory, operating method of semiconductor memory, and system

An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Provided is a memory device in which the decrease of the effective bandwidth caused by the refresh operation of the memory device has been solved, a memory controller of the memory device, and a memory system thereof. A memory device that is operated in response to a command from a memory controller has a plurality of banks that respectively have memory cores including memory cell arrays and decoders and are selected by bank addresses; and a control circuit, which, in response to a background refresh command, causes the memory cores within refresh target banks set by the memory controller to successively execute refresh operation a number of times corresponding to refresh burst length that is set by the memory controller, and, in response to a normal operation command, further causes the memory cores within banks other than the refresh target banks and selected by the bank addresses to execute normal memory operation corresponding to the normal operation command, during the refresh operation executed by the memory cores within the refresh target banks.

Memory device, memory controller and memory system

Semiconductor memory device, and method of controlling the same

A semiconductor memory comprising an address transition detection circuit for detecting a transition of an address and outputs an address detection signal; an address input circuit for inputting an input address based upon the address detection signal; a command judgment circuit for decoding a command signal input and outputting a command judgment signal; a redundancy circuit for making a redundancy judgment based upon a redundancy judgment signal indicating timing of a redundancy judgment, wherein the redundancy circuit includes a redundancy judgment speed-up circuit for controlling an output of the redundancy judgment signal based upon a predetermined command signal.

Semiconductor memory, method of controlling the semiconductor memory, and memory system

A semiconductor memory device includes a DRAM memory core circuit including a word line, a power supply circuit configured to operate in a selected one of a first state and a second state to generate a predetermined power supply voltage for provision to the DRAM memory core circuit, the power supply circuit consuming a larger electric current in the first state than in the second state, and a control circuit configured to control the power supply circuit such that the power supply circuit is shifted from the first state to the second state, and is then brought back to the first state during a period from activation of the word line to deactivation of the word line.

Semiconductor memory device with reduced current consumption

A semiconductor device includes a memory cell array, in which bit lines intersect word lines to form a memory cell. Representative pads are selected from among pads. Data input to the representative pads is decompressed to data corresponding to all of the pads, and is written in corresponding memory cells. The data is read and divided into number of groups corresponding to number of the representative pads. It is determined whether the data in each group coincide with the data input to the representative pads. Output to the representative pads is controlled based on a result of the determination.

Semiconductor device and method for testing semiconductor device

A core control circuit outputs operation control signals to a memory core in order to perform refresh operations in response to an internal refresh request from a refresh request generating circuit and an external refresh request. The core control circuit sets the number of memory cells each subjected to the refresh operation in response to the external refresh request larger than the number of memory cells each subjected to the refresh operations in response to the internal refresh request. By relatively increasing the number of memory cells each subjected to the refresh operation in response to one external refresh request, the number of external refresh requests required to refresh all memory cells can be reduced. Accordingly, the frequency with which the external refresh request is supplied to the semiconductor memory can be lowered, which can improve access efficiency.

Semiconductor memory

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Kawasaki, Japan

Tomohiro Kawakubo