Fujitsu Corporation

Nec Corporation

Renesas Electronics Corporation

Asahi Glass Company, Limited

Tomohiro Hayashi

Katsumi Hayashi

Hiroyuki Itoh

Shogo Shibazaki

Shinpei Komatsu

Masaaki Mitani

Masaru Takehara

Yumi Ishii

Yutaka Sekine

Mitsuhiro Ura

Takuji Ishii

Takashi Obata

Hiroshi Ohsato

Kazuhiko Saitou

Yoshihiro Takamatsuya

Yoshiki Okumura

Takeshi Nagase

Shinkichi Gama

Chitoshi Suzuki

Takayuki Sasaki

Hiraku Chakihara

Yoshiyuki Kawashima

Hiroshi Wada

Takashi Ito

Naoya Torii

Hisashi Sato

Katsuhiko Shimizu

Yoshinori Toyota

Souichi Okada

Chikahiro Deguchi

Koji Ogata

Teruhiko Yasuda

Yoshinori Shimogai

Yasuhito Adachi

Tomoshige Senoo

Kazuhiko Saito

Yumi Fujiwara

A method for manufacturing a semiconductor device includes a step of reducing a thickness of a silicon oxide film embedded in an element isolation trench including fins in order to form protruded fins. In the step, the silicon oxide film is etched while covering part of an upper surface of the silicon oxide film with a resist pattern. At this time, the resist pattern is formed such that a distance between the fin and the resist pattern is equal to or less than a predetermined interval which is an arrangement interval of the plurality of fins.

Method for manufacturing semiconductor device including fin-structured transistor

In a split-gate MONOS memory including a FINFET, occurrence of erroneous write in an unselected cell due to electric field concentration at an upper end of a fin is prevented, and thus reliability of a semiconductor device is improved. An insulating film is formed between an upper surface of a fin and each of a control gate electrode and a memory gate electrode in a memory cell region, so that in a gate insulating film of each of a control transistor and a memory transistor, thickness of a portion on the fin is larger than thickness of a portion covering side surfaces of the fin. The insulating film having a bird's beak at its end portion is formed to round a corner of the fin.

Semiconductor device and method of manufacturing the same

Improvements are achieved in the characteristics of a nonvolatile memory. In plan view, in a first isolation region which is an element isolation region surrounded by a first fin, a second fin, a memory gate electrode, and another memory gate electrode, a protruding portion is provided. In a second isolation region which is the element isolation region overlapping the memory gate electrode in plan view, a second isolation portion is provided to set the protruding portion higher in level than the second isolation portion. In a step of lowering a top surface of the element isolation region located between the first and second fins, a part of the element isolation region located between the first and second fins is covered with a mask film to form the protruding portion. Using the protruding portion, a short circuit between the memory gate electrodes due to a gate residue is prevented.

Semiconductor device

An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, using a control gate electrode and a memory gate electrode which are formed over a semiconductor substrate as a mask, n-type impurity ions are implanted from a direction perpendicular to a main surface of the semiconductor substrate. Then, using the control gate electrode, the memory gate electrode, and first and second sidewall spacers as a mask, other n-type impurity ions are implanted from a direction inclined relative to the direction perpendicular to the main surface of the semiconductor substrate.

Method of manufacturing semiconductor device having an implanting from a second direction inclined relative to a first direction

A semiconductor device having improved reliability is disclosed. In a semiconductor device according to one embodiment, an element isolation region extending in an X direction has a crossing region that crosses, in plan view, a memory gate electrode extending in a Y direction that intersects with the X direction at right angles. In this case, in the crossing region, a width in the Y direction of one edge side, the one edge side being near to a source region, is larger than a width in the Y direction of the other edge side, the other edge side being near to a control gate electrode.

Semiconductor device and manufacturing method thereof

A process for producing a polyether polyol which can form low viscosity rigid foamed synthetic resins excellent in strength, dimensional stability and flame retardancy, can give a low viscosity polyol system solution containing water instead of HFCs as a blowing agent with good miscibility with isocyanate compounds and can form good rigid foamed synthetic resins by spraying, which polyether polyol is produced by reacting a phenol component (molar ratio 1) selected from phenol and phenol derivatives having a hydrogen atom at one or more ortho-positions to the phenolic hydroxyl group, an aldehyde component (molar ratio 0.3 to 0.9) selected from formaldehyde and acetoaldehyde and an alkanolamine component (molar ratio 1.5 to 3.5) selected from monoethanolamine, diethanolamine and 1-amino-2-propanol and then adding an alkylene oxide to the resulting reaction product.

Process for producing polyether polyol and process for producing rigid foamed synthetic resin using same

A differential latch comprising a data holding transistor, the differential latch comprising: a resetting transistor that is connected to a gate electrode of the data holding transistor and is controlled by a reset signal; and a switching transistor that is connected to the gate electrode of the data holding transistor and is controlled by a switch signal, being an inverted version of the reset signal.

Differential latch, differential flip-flop, LSI, differential latch configuration method, and differential flip-flop configuration method

An inter-phase skew detection circuit includes a frequency division circuit that frequency-divides N-phase clocks to be measured at predetermined timings so as to generate N+2 frequency-divided clocks; a phase comparison target clock generation circuit that generates N phase comparison target clocks by using predetermined N frequency-divided clocks among the N+2 frequency-divided clocks; a phase comparison reference clock generation circuit that generates N reference clocks by using the N+2 frequency-divided clocks, in accordance with predetermined combinations between the N+2 frequency-divided clocks and an operation criterion; and a phase comparison circuit that detects respective phase differences between the N phase comparison target clocks and the corresponding N reference clocks.

Inter-phase skew detection circuit for multi-phase clock, inter-phase skew adjustment circuit, and semiconductor integrated circuit

To provide a method for producing a polymer-dispersed polyol which has high compatibility with a polyol for rigid polyurethane foams and is excellent in storage stability and which provides good heat-insulating performance when it is formed into a rigid polyurethane foam. Also a method for producing a polymer-dispersed polyol for rigid polyurethane foams, having polymer particles dispersed in a polyol, which comprises polymerizing a monomer having a polymerizable unsaturated group in a polyol (X), wherein the polyol (X) contains a polyether polyol (Y) having an oxyethylene group content of at least 10 mass %, and the monomer having a polymerizable unsaturated group contains a fluorinated acrylate or a fluorinated methacrylate.

Method for producing polymer-dispersed polyol

To provide a flexible polyurethane foam having good vibration characteristics and suitable particularly for a seat for an automobile. A flexible polyurethane foam obtainable by reacting a polyol composition with a polyisocyanate compound in the presence of a catalyst, a blowing agent and a foam stabilizer, characterized in that the polyol composition comprises a high molecular weight polyoxyalkylene polyol (A1) and a polymer-dispersed polyol (A2) containing fine polymer particles in the high molecular weight polyoxyalkylene polyol (A1), and at least part of the fine polymer particles contained in the polymer-dispersed polyol (A2) are fine polymer particles having silicon atoms.

Flexible polyurethane foam, process for its production, and seat for automobile using the flexible polyurethane foam

To provide a flexible polyurethane foam having good vibration characteristics and suitable particularly for a seat for an automobile. A flexible polyurethane foam obtained by reacting a polyol composition with a polyisocyanate compound in the presence of a catalyst, a blowing agent and a foam stabilizer, characterized in that the polyol composition comprises a high molecular weight polyoxyalkylene polyol (A) and a polymer-dispersed polyol (C) containing fine polymer particles in a high molecular weight polyoxyalkylene polyol (B), and at least part of the fine polymer particles are fine polymer particles obtained by polymerizing a monomer containing a fluorinated acrylate or a fluorinated methacrylate.

A phase locked loop circuit includes a voltage controlled oscillator having an oscillating characteristic value changed by a switching signal. A characteristic controller supplies the switching signal to the voltage controlled oscillator to increase the oscillating characteristic value according to elapse of time. The voltage controlled oscillator oscillates according to both of the oscillating characteristic value and a frequency control signal. Even if the frequency control signal is equal to a power source level at the beginning of supplying electric power, the phase locked loop can be locked in a target frequency.

Phase locked loop circuit and control method thereof

Data transferred from a host computer to a memory device is written into sectors whose addresses in a memory area are decoded by a decode table. Old data to be updated by the above data is erased or marked with erase flags. At a predetermined point of time, in order to create free areas, necessary data is evacuated to a primary memory media and unnecessary data indicated by erase flags is erased by a unit of predetermined memory size. Part of the memory media which has become defective is marked with a defect flag, and is replaced by an alternate area. In doing so, the decode table is rewritten to arrange the memory area.

Method of writing, erasing, and controlling memory for memory device

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Tokyo, Japan

Tomohiro Hayashi