Hitachi, Ltd.

Tomohiko Shigeoka

Toru Nojiri

Akio Igarashi

Atsushi Sashino

Takehiko Nagano

Atsuhiro Yokoro

Hirokazu Fujiwara

A CPU forced stop signal is used as means for stopping execution of a program executed on a ROM by a CPU of a target system. A time required for stopping the CPU from the issuance of the CPU forced stop signal between an ICE device and the CPU is considered and set, and a CPU forced stop signal issuance position which is prior to a stop target position is determined. Based on a real-time tracing function of the CPU, at an issuance position and timing of the CPU forced stop signal on the execution of the program, the CPU forced stop signal is issued, the CPU is stopped, and the event is acquired. By this means, an arbitrary number of events of the program can be acquired regardless of the number of breakpoint registers.

Program failure analysis system, failure analysis method, and emulator device

Object information is read that denotes a load state of the object from storage and selects an object having a load that is lower than a predetermined value. Then, a reference to an object allocation control part is returned that allocates the selected object to a destination as a response through communicating means. In allocating an object, the object information is read from the storage to select an object having a load that is lower than a predetermined value. Then, a reference to a dispatcher is returned that executes the selected object to the destination as a response through the communicating means. In executing the object, the object information is read from the storage and executes the object if the object has a load that is lower than a predetermined threshold value.

Load balance control method and load balance control apparatus in data-processing system

Growing community of inventors

Yokohama, Japan

Tomohiko Shigeoka