Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Tomohiko Imada

Yoshihisa Imori

Hiroaki Kishi

Akito Shimizu

Morihiko Ikemizu

Seiji Watanabe

Toyokazu Shibata

Yasuhisa Shintoku

Atsushi Hosokawa

Kumiko Karouji

Shinya Shimamura

A semiconductor device includes a molded body and an interconnection layer. The molded body includes a semiconductor chip, at least one terminal body disposed around the semiconductor chip and a resin member provided between the semiconductor chip and the terminal body. The molded body has a first surface, a second surface opposite to the first surface and a side surface connected to the first and second surfaces. The interconnection layer is provided on the first surface of the molded body. The interconnection layer includes an interconnect electrically connecting the semiconductor chip and the terminal body. The terminal body has first and second contact surfaces. The first contact surface is exposed at the first or second surface of the molded body. The second contact surface is connected to the first contact surface and exposed at the side surface of the molded body.

Semiconductor device and method for manufacturing same

According to one embodiment, a semiconductor device includes a first semiconductor chip, a heat dissipation member provided on one surface of the first semiconductor chip and connected to the first semiconductor chip, and a sealing resin sealing the first semiconductor chip and the heat dissipation member. The heat dissipation member includes mutually interlaced metal fibers and a thermosetting resin.

Semiconductor device

A semiconductor integrated circuit design supporting system has a memory unit which stores cell information containing the number of power supply pads formed at a chip as well as names and the number of a plurality of IO cells, and a drive factor definition file defining a drive factor of each of the plurality of IO cells, a pad laying out section which tentatively lays out the power supply pads and input-output pads corresponding to the IO cells, using the cell information, a package virtual designing section which prepares a package drawing based on coordinates of the power supply pads and the input-output pads, which have been tentatively laid out, an electric characteristics data calculating section which calculates inductance of the power supply pads, using the package drawing, and a noise risk calculating section which calculates noise risk of each of the input-output pads, using the inductance and the drive factor definition file.

Semiconductor integrated circuit design supporting method, semiconductor integrated circuit design supporting system, and computer readable medium

A system for designing connecting terminals of a semiconductor device, having a power supply cell arranging unit configured to arrange power supply cells at some of I/O slots formed in a semiconductor chip, an I/O signal cell arranging unit configured to arrange I/O signal cells at some of the I/O slots where the power supply cells are not arranged, a first connecting net generator configured to generate a first connecting net connecting the I/O slots to bumps formed on the semiconductor chip, a second connecting net generator configured to generate a second connecting net connecting the bumps to external electrodes formed on a package base, and a verifier configured to verify whether the power supply cells, I/O signal cells, and first and second connecting nets violate predetermined design rules.

System, method and computer program product for designing connecting terminals of semiconductor device

Growing community of inventors

Ebina Kanagawa, Japan

Tomohiko Imada