Fujitsu Corporation

Tomoharu Miyadai

Syoji Yamaguchi

Ayumi Naito

A shift operation circuit includes: shift circuits respectively coupled internal buses whose bit numbers partially overlap, each shift circuit receiving one of sets of divided data obtained by dividing input data and one of shift amount signals and outputting the corresponding divided data to a range shifted based on a shift amount represented by the corresponding shift amount signal from a reference bit position in the corresponding internal bus; a shift control circuit configured to output, during a first mode, shift amount signals whose shift amounts are common to the shift circuits, and configured to convert, during a second mode, a shift amount signal for each shift circuit, into a shift amount signal representing a shift range whose bit numbers do not overlap in the internal buses; and a bit selecting circuit configured to select valid divided data from bits whose bit numbers overlap in the internal buses.

Shift operation circuit and shift operation method

A data processing circuit inputs and connects a plurality of digital audio input channels in parallel, time-divisionally individually processes data of each input channel at every period Tu that is determined by a standardized united sampling frequency 44.1 kHz, thereafter, performs a designated mixing, and outputs mixed data from a D/A converter 44 to a line. When the united sampling frequency 44.1 kHz and a sound source sampling frequency of audio data differ, an interpolating process is executed.

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Yokohama, Japan

Tomoharu Miyadai