Mitsubishi Denki Kabushiki Kaisha

Renesas Technology Corp.

Mitsubishi Chemical Industries Limited

Mitsubishi Kasei Corporation

Tomoharu Mametani

Yukihiro Nagai

Hiroaki Nishimura

Takeshi Kishida

Akinori Kinugasa

Jiro Matsufusa

Shigenori Kido

Yoji Nakata

Ichiro Arimoto

Masami Yamamoto

Ritsuko Tsutsumi

Konoe Miura

Tameichi Ochiai

Yasuhiro Kameyama

Takashi Okabe

Tooru Koyama

Masahiro Shimizu

Katsuhiro Tsukamoto

Hajime Arai

Heiji Kobayashi

In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.

Semiconductor device having a potential fuse, and method of manufacturing the same

A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.

Semiconductor device having test mark

There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

Semiconductor device, and method of manufacturing the same

A contact structure is formed with no voids in an interlayer insulation film and good surface planarity. A first insulation film ( ) formed of p-TEOS is deposited to cover a substrate ( ) and wires ( ) formed on the substrate ( ). A second insulation film ( ) which is coating glass is formed by SOG. The surface is etched back from the opposite side to the substrate ( ); therefore, the second insulation film ( ) is etched. The etching is stopped at the point where the surface ( ) of the first insulation film ( ) on the wires ( ) is exposed. This ensures good surface,planarity. A third insulation film ( ) is stacked on top of the second insulation film ( ), and portions of the third insulation film ( ) above the wires ( ) are isotropically etched to form openings ( ). At this time, the isotropic etching does not extend over the second insulation film ( ).

Method of manufacturing contact structure

Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (,) in which impurity is diffused is deposited on the entire surface including the inside of a hole (,A). An etching process of the polysilicon layer (,) is performed to form a storage node electrode composed of the polysilicon layer (,) remaining on the bottom and side of a groove for metallization (,) and in the hole (,A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (,), and a plug part disposed in the hole (,A). The storage node electrode is electrically connected via the plug part to a diffused region (,) of a semiconductor substrate (,).

Method of manufacturing semiconductor device

There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC. The present invention provides a method of manufacturing a semiconductor device including a basic dielectric layer formation step for forming a basic dielectric layer from a first dielectric material, a stopper film formation step for forming on the basic dielectric layer an etch stopper film from a second dielectric material differing from the first dielectric film, a sacrificial dielectric layer formation step for forming on the etch stopper film a sacrificial dielectric layer from the first dielectric material, a space formation step for forming a storage node formation space by removal of a predetermined area from the sacrificial dielectric layer until the etch stopper film becomes exposed, a storage node formation step for forming in the storage node formation space a storage node from a capacitive material, and a sacrificial dielectric layer removal step for removing the sacrificial dielectric layer surrounding the storage node by means of an etching operation suitable for removal of the first dielectric material.

Method of manufacturing a semiconductor device

An improved semiconductor device which prevents a short circuit between a wiring layer and a semiconductor substrate, caused by the penetration of a contact hole, will be provided. A lower conducting layer is formed on a second interlayer insulating film. A third interlayer insulating film covers lower conducting layer. A contact hole is formed in third interlayer insulating film in order to connect an upper conducting layer and lower conducting layer. A stopper layer of silicide or metal is formed below contact hole between the surface of a semiconductor substrate and lower conducting layer.

Semiconductor device with improved interconnection

On a semiconductor substrate, a first circuit and a second circuit are provided with a space therebetween. The first circuit and the second circuit are connected to each other by a fuse portion. In the middle of the fuse portion, a connecting portion is interposed, which is made of a material highly resistant to corrosion. Accordingly, an improved semiconductor device with a corrosion-resisting fuse portion is accomplished, which ensures the layout to be designed much more freely.

Semiconductor device with moisture resistant fuse portion

In a manufacturing process of a MOS FET having a C-MOS structure, lightly doped n- diffused layer is formed for source/drain regions in n channel and p channel transistor regions respectively. A p+ diffused layer is further formed for source/drain regions in a p channel transistor region. By a heating process, the n- layer is outweighed by diffusion of p type impurities in the p channel transistor region, and the source/drain current of the p channel MOS FET is secured.

Manufacturing process of a MOS semiconductor device

A thick isolation oxide film is selectively formed on a surface of a silicon substrate so as to isolate an element formation region. Ions are implanted into a region in silicon substrate through the thick isolation oxide film. Thus, retrograde wells, having impurity concentration peak positions are formed in the region of silicon substrate positioned under the isolation oxide film. Then, an upper part of the isolation oxide film is removed away to form an isolation oxide film with a reduced thickness. Isolation oxide film has a reduced isolation length L. Thus, a semiconductor device is provided, which permits restriction of the narrow channel effect and the substrate biasing effect when the size of elements is reduced.

Method of manufacturing semiconductor device with retrograde wells

A are a semiconductor memory device excellent memory characteristics of which can be obtained without deteriorating a characteristic of a transistor for use in a peripheral circuit even when a memory cell array region and a peripheral circuit region differ from each other in wiring pattern density and a manufacturing method therefor. The semiconductor memory device includes a dummy pattern formed between and at predetermined distance from gate electrodes of a transfer gate transistor in the peripheral circuit region. As a result, precision in dimension of the gate electrode in the peripheral circuit portion is improved to achieve excellent memory characteristics without deteriorating the transistor

Semiconductor device having dummy wiring pattern therein and

A LOCOS isolation film is formed on a major surface of a semiconductor substrate. Thereafter, a new surface of the semiconductor substrate is exposed by wet etching. A resist pattern is formed on the exposed new surface. A part of the LOCOS isolation film is removed using this resist pattern, to expose the surface of the semiconductor substrate. This unsymmetrical LOCOS isolation film increases the effective area of the surface of the semiconductor substrate and preserves predetermined dielectric resistance.

LOCOS type field isolating film and semiconductor memory device formed

Disclosed herein is an antistatic photo-resist containing an antistatic agent. Since antistatic photo-resist according to the present invention is hardly charged, it can be suitably used as a mask in implanting ions into semiconductor substrate.

Growing community of inventors

Tokyo, Japan

Tomoharu Mametani