Matsushita Electric Industrial Co., Ltd.

Panasonic Corporation

Tomoharu Kawada

Kazuki Ninomiya

Akifumi Nagao

Jiro Miyake

Toshinori Maeda

Hiroaki Ishii

Yukiyoshi Nagasawa

Keiichiro Wada

A diversity receiving device includes a processing circuit in which receiving units, AFC and synchronizing units, and demodulating units for a plurality of systems are connected, received signal intensity detecting unitsandthat detect the intensities of output signals of the respective receiving units so as to output reception intensity detection signals, a control unit that determines to select one system as a synthesis pattern of demodulation signals based on a predetermined judgment criterion according to the respective reception intensity detection signals or to select a plurality of systems so as to add demodulation signals and outputs a plurality of clock interruption control signals requesting the interruption of a clock supply to unselected systems and synthesis pattern selection signals designating a synthesis pattern of demodulation signals of the selected system, a plurality of clock supply units that interrupt the clock supply to the AFC and synchronizing units and the demodulating units of the unselected systems according to the clock interruption control signal, and a synthesizing unit that synthesizes demodulation signals of the selected system according to the synthesis pattern selection signals.

Diversity receiving device

A packet synthesizing unit packetizes transmit data and thereby creates a transmit packet data, and more specifically, synthesizes the number of the transmit data indicated by a packet-length information from a packet length controlling unit into a transmit packet data. A frame synthesizing unit appends the packet-length information for transmission to a header of the transmit packet data to thereby create a transmit frame. A wireless transmit unit converts the transmit frame into a wireless transmit signal and wirelessly transmits the wireless transmit signal. In the wireless transmission, the packet length controlling unit controls the packet length of the transmit data according to a transmit rate in the wireless transmit unit. The packet length controlling unit reduces the packet length when the transmit rate is relatively high and extends the packet length when the transmit rate is relatively low. This improves the transmission efficiency and communication quality.

Wireless LAN apparatus for changing packet length according to changing conditions

A memory unit includes a plurality of read bit lines, a plurality of read word lines, a plurality of write bit lines, and a plurality of write word lines. An array of memory cells are connected to the read bit lines, the read word lines, the write bit lines, and the write word lines. Each of the memory cells includes at least two input sections, at least two output sections, and a memory element. The output sections are connected to at least two of the read word lines, respectively, and output data from the memory element to one of the read bit lines in response to signals on the read word lines. The input sections are connected to at least two of the write word lines, respectively, and output data from one of the write bit lines into the memory element in response to signals on the write word lines. A plurality of decoders connected to the read word lines decode a read address signal into output signals, respectively, which are fed to the read word lines. A plurality of decoders connected to the write word lines decode a write address signal into output signals, respectively, which are fed to the write word lines.

Semiconductor memory unit having overlapping addresses

A microprocessor system which comprises an arithmetic logic unit for generating flags, a flag update detector for outputting a flag update detecting signal, a status register coupled to the flag update detector and the arithmetic logic unit for receiving the flag update detecting signal and a flag outputted from the arithmetic logic unit, a first address outputting portion coupled to the flag update detector and the status register for receiving the flag update detecting signal, a flag outputted from the status register, a target instruction address, a next instruction address and a branch condition for determining according to the flag received from the status register whether or not the branch condition is met, and for outputting first and second address candidates selected from the target instruction address and the next instruction address according to the flag update signal and to whether or not the branch condition is met, and a second address outputting portion coupled to the first address outputting portion and the arithmetic logic unit for receiving the first and second address candidates outputted from the first address outputting portion, the branch condition and the flag outputted from the arithmetic logic unit, for determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met, and for outputting the target instruction address or the next instruction address as an instruction fetch address on the basis of a result of determining according to the flag received from the arithmetic logic unit whether or not the branch condition is met.

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Osaka, Japan

Tomoharu Kawada