Fujitsu Corporation

Socionext Inc.

Fujitsu Semiconductor Limited

Fujitsu Microelectronics Limited

Tomoharu Awaya

Tomoyuki Yamada

Takayoshi Minami

Shigetoshi Takeda

Koji Banno

Fumio Ushida

Isao Fukushi

Jun Nagayama

Yoshinori Okajima

Masamichi Kamiyama

Masahito Isoda

Masaya Sugimoto

Tsuyoshi Koyashiki

A semiconductor device provided on a semiconductor substrate includes an element region including an element, a moisture-resistant frame surrounding the element region, an insulating layer provided between the moisture-resistant frame and an outer peripheral edge of the semiconductor device and on the semiconductor substrate, a first metal line extending along the outer peripheral edge and provided in the insulating layer, and a groove provided in the insulating layer.

Semiconductor device and method of producing semiconductor device

An electronic circuit includes: first circuits each including a first FET having a source supplied with at least one of a first voltage and a second voltage; and a second circuits each of which is associated with a respective one of the first circuits, and generates a back bias voltage applied to the first FET so as to change in accordance with a change of at least one of the first and second voltages.

Electronic circuit and semiconductor device

In a semiconductor device and a write control circuit, a voltage detection unit detects a write voltage supplied to a storage element (electrical fuse element) in which only single writing is electrically performed and, when the write voltage is equal to or more than a predetermined threshold voltage, allows the write control unit to stop writing to the electrical fuse element regardless of the write signal. The above processing permits the write control circuit to suppress false writing caused by the fact that abnormality occurs in a write voltage and it becomes an overvoltage.

Write control circuit and semiconductor device

Semiconductor device, moisture-resistant frame, groove and method of producing semiconductor device

A timing analysis method evaluates a performance of a target circuit that is to be designed, and includes calculating a correlation coefficient r between two arbitrary macro cells that are coupled and form the target circuit based on layout information including an arrangement of macro cells forming the target circuit and correlation information indicating a correlation between two macro cells that are coupled for each of arrangements of macro cell pairs, calculating a distribution function &#x3c3; of a standard deviation of delay times of the two arbitrary macro cells based on the correlation coefficient &#x3c3;, and carrying out a statistical timing analysis of the target circuit based on the correlation coefficient r and the distribution function &#x3c3; of the standard deviation with respect to each of the macro cell pairs forming the target circuit.

Timing analysis method and apparatus, computer-readable program and computer-readable storage medium

A semiconductor memory device including a write control system for controlling data write to a selected memory cell on the basis of a write control signal, an external terminal for test, a write pulse generating circuit for generating a test write pulse on the basis of a set signal given from the external terminal and the write control signal, and supplying it to the write control system. The write pulse generating circuit includes a pulse-width changing circuit for variably setting a pulse width of the test write pulse on the basis of the set signal. The test write pulse width can be freely and precisely set by using the minimum possible number of external terminals for test. A test write pulse width which agrees with the real capacity of high speed devices can be obtained even by using relatively economical, low speed testing equipment.

Semiconductor memory device having a variably write pulse width

A bipolar-transistor type semiconductor memory device including a normal memory cell array, redundancy memory cell array, a redundancy driving circuit, and a redundancy address decision circuit. When the redundancy address decision circuit determines that the input address coincides with the address of a defective circuit portion, the redundancy driving circuit is driven to enable the redundancy memory cell array instead of the normal memory cell array.

Bipolar-transistor type semiconductor memory device having redundancy

A semiconductor memory device having a redundancy configuration including a read circuit for a defective memory address. The read circuit includes a transistor which forms a current switch circuit with a bipolar-transistor of an input buffer circuit. The base electrode of the transistor is connected to the output terminal of a PROM which stores a defective address. The reading operation is carried out by applying a voltage lower than a normally applied voltage to the base electrode of the bipolar-transistor and detecting the base current.

Semiconductor memory device having redundancy configuration with read

A bipolar-transistor type semiconductor memory device having a redundancy configuration includes a memory cell array, a redundancy memory cell array, and an address buffer circuit having a predetermined number of emitter-coupled logic gates which receive input address signals and have an output terminal. Each of the logic gates compares a voltage level of the corresponding input address signal with a voltage level of a reference signal. A group of first decoder lines connected to the predetermined output terminals. A comparator circuit detects whether or not each of the input address signals coincides with each of address signals corresponding to a defective circuit portion and puts a selection signal in accordance with the detection of a coincidence signal. A switching circuit compares a voltage level of the selection signal with a voltage level of a reference signal. A second decoder line is connected to a predetermined output terminal provided in the switching circuit. A predetermined number of diode groups including a predetermined number of first diodes and a second diode are provided. The conductive state of each of the first diodes is determined by a voltage level of the predetermined first decoder line, the conductive state of the second diode is determined by a voltage level of the second decoder line. Accordingly, the memory cell array is selected through the predetermined diode groups in accordance with the input address signals when the comparator circuit does not output the selection signal. Otherwise the redundancy memory cell array is selected.

Semiconductor memory device having diode matrix type decoder and

A bipolar-transistor type RAM device, particularly an ECL type RAM device, includes a memory cell array, an address receiving circuit, a normal memory cell selecting circuit, and a redundancy configuration. The redundancy configuration includes a redundancy memory cell array, a defective memory address storing circuit, an address comparing circuit, and a redundancy memory cell selecting circuit. The address comparing circuit directly receives the address signal and the defective memory address signal. The normal memory cell selecting circuit is energized when the address signal does not equal the defective memory address signal. Otherwise, the redundancy memory cell selecting circuit is energized.

Bipolar-transistor type random access memory device having redundancy

A semiconductor memory device which includes a high potential source, a low potential source, and a word line driver portion which makes the potential of selected word lines a selection level lower by a predetermined potential than the high potential source. Memory cells are connected to the word lines. A first low potential source or a second potential source is connected to the low potential source. A plurality of transistors are provided in the word line driver portion so as to connect a plurality of stages. When the memory has a sufficient power source margin, the word line driver is formed as a two-stage device so as enable high speed operation. When the memory has an unsufficient power source margin, the word line driver is formed as a one-stage device so as to ensure a sufficient power source margin.

Growing community of inventors

Kawasaki, Japan

Tomoharu Awaya