Powerchip Semiconductor Manufacturing Corporation

Powerchip Technology Corporation

Tomofumi Kitani

Hideki Arakawa

A failure bit count (FBC) circuit for memory array is provided. The memory array includes pages each having plural sectors and a redundancy column. The FBC circuit includes FBC units, in which each FBC unit is respectively coupled to each sector for providing a failure bit count current; a redundancy FBC unit coupled to the redundancy column and provides a redundancy current; a switch having a first end and a second end capable of being switched to couple to one of outputs of the FBC units to receive the failure bit count current from one of the FBC units; a comparator having a first input end that receives a reference current, and a second input end that receives a measurement current obtained by adding the failure measurement current and the redundancy current, and an output end outputting a judge signal to indicate a number of failure bits for each sector.

Failure bit count circuit for memory and method thereof

An oscillator circuit is provided. A first and a second cycle generating units, and a first and a second duty generating units are included. An SR latch, receiving outputs the first and second cycle generating units. In the SR latch, an output is provided to the first cycle generating unit and the third duty generating, and a contemporary output is provided to the second cycle generating unit and the second duty generating unit. A logic circuit receives the outputs of the first and the second duty generating units and the output and the contemporary output of the SR latch to generate a clock signal. The first and the second cycle generating units are respectively operated to provide the even and odd cycle times of the clock signal. The first and the second duty generating units are respectively operated to provide the even and odd duties of the clock signal.

Oscillator circuit

A comparator () compares a pad voltage with a reference voltage (Vref) to output a voltage (VCCOK), and a comparator () compares a low voltage with a reference voltage (Vref) to output a voltage (VDDOK). A power-on circuit () includes a timer circuit () and starts a reference voltage generation circuit () after the power switch control circuit is started, and then starts the comparator (). After the comparator () is started, a controller () starts a voltage down converter () when the voltage (VCCOK) is at the H level, and turns on a MOS transistor (Q) when the voltage (VCCOK) is at the L level. A power-on circuit () includes a timer circuit () and starts a reference voltage generation circuit () after the voltage down converter () is started, and then starts a comparator (). After the comparator () is started, the controller () enters the standby state.

Power switch control circuit and control method thereof

A stable reference voltage that can be supplied in a layout area smaller than prior art is provided. A current-voltage convertor includes a first current mirror circuit including a first MOS transistor, a second MOS transistor in a pair, and an output resistor; and a depletion type N-channel MOS transistor, inserted between a first voltage to be input and the first MOS transistor and the second MOS transistor, and having a gate to which an output voltage from the output resistor is fed back. When a reference current is input to the first MOS transistor, the output voltage is generated by a current corresponding to the reference current flowing into the second MOS transistor and the output resistor. In addition, a reference voltage generator including the current-voltage convertor is provided to output a reference voltage based on the output voltage of the current-voltage convertor.

Current-voltage convertor, reference voltage generator and non-volatile semiconductor storage device

An offset voltage Vis compensated in a digital to analog (DA) convertor using a switched-capacitor circuit, including an input circuit, a first differential amplifier, and an offset cancel circuit comprising a second differential amplifier, in a sampling period, when the second feedback circuit is short, an output voltage of the first differential amplifier is input to a first end of a first capacitor, the offset cancel circuit feeds back a reference voltage to an inverting input terminal of the second differential amplifier and a second end of the first capacitor from an output of the second differential amplifier, in a holding period, when the second feedback circuit is not short, the offset cancel circuit inputs a differential voltage between the reference voltage and the output voltage of the first differential amplifier into an inverting input terminal of the first differential amplifier via a second capacitor.

Digital to analog convertor, failure bit number detector and non-volatile semiconductor storage device

A page buffer circuit includes a latch circuit that temporarily stores data when data is written in or read out from a memory cell through a bit line, the page buffer circuit is configured using a switched capacitor circuit. The page buffer circuit includes a first capacitor connected to a sense terminal connected to one end of the latch circuit, a second capacitor connected to the bit line, a first switch interposed between the sense terminal and the second capacitor, a second switch interposed between the sense terminal and a supply voltage, a first transistor including a control terminal and a first element terminal connected to both terminals of the first switch in parallel, a second transistor including first and second element terminals connected between a second element terminal of the first transistor and a ground, and a control circuit controlling the first and second switches and the second transistor.

Page buffer circuit and nonvolatile storage device

A high voltage generating circuit includes a charge pump circuit and an output voltage control circuit. The charge pump circuit raises a voltage to a high voltage higher than a power supply voltage. The output voltage control circuit controls the voltage to make the raised high voltage to be a predetermined target voltage. The output voltage control circuit includes at least two offset free comparator circuits, or at least one offset free comparator circuit and at least one differential amplifier. The offset free comparator circuit includes a coupling capacitor, a differential amplifier and a plural switch. The coupling capacitor inputs a voltage corresponding to the high voltage. The differential amplifier compares a voltage from the coupling capacitor with a predetermined reference voltage and outputs a comparison result voltage to the charge pump circuit. The switches are connected to the differential amplifier to cancel an offset of the differential amplifier.

Voltage generating circuit and regulator circuit for precisely control predetermined high voltage

A negative reference voltage generating circuit includes a switched capacitor circuit having a capacitor connected to a first and a second nodes, a first and a second switches connected to the first node, a third and a fourth switches connected to the second node; and a control circuit, generating a first to a fourth control signals to control the first to the fourth switches respectively. The control circuit applies a preset positive reference voltage to the first node to charge the capacitor during a first period, and outputs a negative voltage from the second node based on the voltage charged to the capacitor during a second period different from the first period. By repeating the first and the second periods, an inverting negative voltage of the positive reference voltage that is outputted from the second node is used as a negative reference voltage.

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Tokyo, Japan

Tomofumi Kitani