Kabushiki Kaisha Toshiba

Tomofumi Fujimura

Kosuke Yanagidaira

Yuui Shimizu

Naofumi Abiko

A nonvolatile semiconductor memory device includes memory cells arranged into memory strings with word lines each connected to a different memory cell of the memory strings. The device also includes bit lines each connected to a different memory string and a column decoder connected to the bit lines. The column decoder includes sense amplifiers, data latches, and a data bus connecting sense amplifiers and data latches. The data bus is divided into at least two portions and includes a first portion connected to a second portion by a switch.

Nonvolatile semiconductor memory device having a column decoder with multiple data bus portions connected via a switch

A memory includes stacking chips. The chip includes a pad commonly connected to the chips and receiving an enable signal that enables access to each chip. The chip includes a chip address memory that can store a chip address. The chip includes a determining part comparing a select address to the chip address for determining whether they match each other. The chip includes a control-signal setting part setting the control signal inputted to the chip itself to be valid or invalid depending on a determination made by the determining part. The chip includes a chip-address setting part determining whether the chip address is stored in the chip address memory depending on number of fail bits. The device includes a memory controller allocating respectively different ones of the chip addresses to the chips based on the number of fail bits.

Semiconductor memory device including a plurality of stacked semiconductor memory chips

The present invention provides a semiconductor memory device that can minimize the widening of the threshold voltage distribution of cell transistors during a data erasing operation. The semiconductor memory device includes: a memory cell unit that is formed with nonvolatile memory cells connected in series, is divided into at least two groups each including one or more of the nonvolatile memory cells, and has one end connected to a source line and the other end connected to a bit line, word lines being connected to the gates of the nonvolatile memory cells, the voltages of the word lines being controlled to store data from the bit line or output stored data onto the bit line; and a voltage applying circuit that applies voltages to the word lines of the nonvolatile memory cells, applying a first voltage to the word lines of the nonvolatile memory cells of the group located closer to the bit line, and applying a second voltage to the word lines of the nonvolatile memory cells of the group located closer to the source line, with respect to the two adjacent groups of the memory cell unit, when a data erasing operation is performed to erase data stored in the nonvolatile memory cells forming the memory cell unit, the second voltage being higher than the first voltage.

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Kanagawa, Japan

Tomofumi Fujimura