Kabushiki Kaisha Toshiba

Toshiba Electronic Devices & Storage Corporation

Tomoaki Yabe

Shinji Miyano

Kenji Numata

Katsuhiko Sato

Ryo Haga

Akihito Tohata

Tohru Furuyama

Nobuaki Otsuka

Osamu Wada

Atsushi Kawasumi

Masataka Matsui

Shigeyuki Hayakawa

Hideki Takeuchi

Keniti Imamiya

Gou Fukano

Kimimasa Imai

Mitsuhiro Yano

Kouichi Satou

A semiconductor device includes a substrate; a first semiconductor layer above the substrate, a second semiconductor layer between the substrate and the first semiconductor layer, first and second conductors, an electrode, and first and second insulating films. The first and second semiconductor layers have a first end and a second end opposite to the first end. The first conductor is connected to the first ends of the first and second semiconductor layers. The second conductor includes a first portion connected to the second ends of the first and second semiconductor layers and a second portion positioned inside the substrate. The electrode faces portions of first and second semiconductor layers between the first end and the second end thereof. The first insulating film is provided between the first semiconductor layer and the electrode; and the second insulating film is provided between the second semiconductor layer and the electrode.

Semiconductor device

A semiconductor memory device operates by using a fixed power and a variable power. The device includes a plurality of word lines which select rows of a memory cell array, a plurality of word line drivers each of which is connected to a corresponding one of the word lines and includes a first CMOS gate, a first cutoff switch which is connected between a fixed power terminal and a power terminal of the first CMOS gate and cuts off the fixed power in a sleep mode, a switching circuit which is connected to the plurality of word lines and connects the plurality of word lines to a ground terminal in the sleep mode, and a power control circuit which generates the variable power by using the fixed power and sets the variable power to 0 V in the sleep mode.

Semiconductor memory device

A semiconductor memory device includes first and second cell arrays which have memory cells arrayed in row and column directions, first and second bit lines which are connected to the memory cells arrayed in the column direction, and first and second sense amplifiers which are connected to the first, second bit lines, respectively. The device also includes first and second dummy cell arrays which have dummy cells arrayed in the row and column directions, a dummy word line which is connected to the dummy cells arrayed in the row direction, first and second dummy bit lines which are connected to the dummy cells arrayed in the column direction and receive an output from the dummy word line, and first and second sense amplifier activation circuits which activate the first, second sense amplifiers in accordance with first and second control signals output from the first and second dummy bit lines, respectively.

Semiconductor memory device having replica circuit

This semiconductor memory device comprises a plurality of sub-arrays with a plurality of memory cells arranged in matrix form. Each local bit line is connected to a plurality of memory cells that are arranged in column direction in the sub-arrays. In addition, a global bit line is connected to the plural local bit lines. A column decoder is connected to the global bit line. The global bit line extends from the column decoder toward the plurality of sub-arrays, and it is cut before the furthest sub-array formed in the furthest region from that column decoder.

A semiconductor memory device includes a plurality of memory cells each including a first inverter and a second inverter, a first storage node connected to an output terminal of the first inverter and an input terminal of the second inverter, and a second storage node connected to an input terminal of the first inverter and an output terminal of the second inverter, a word line connected to the memory cells, and a plurality of bit lines connected to the memory cells, respectively. Input data is written to a selected memory cell, and data read from a non-selected memory cell is written again to the non-selected memory cell in write operation.

Semiconductor memory device and control method thereof

A semiconductor memory device including a first memory to which a first address and first input data are input, and which outputs first output data, a content-addressable memory to which the first address is input as a search address, and which performs a search to determine whether or not the first address and a defective address coincide with each other and, when the first address and the defective address coincide with each other, outputs a second address and a control signal, a second memory which, when the second address is input thereto, outputs redundant data corresponding to the second address, and a multiplexer which, when the control signal is input thereto, switches the output data from the first output data to the redundant data, and outputs the redundant data to an input/output terminal.

Semiconductor memory device and redundancy method thereof

A semiconductor memory device includes a plurality of word lines, first and second bit lines, a plurality of memory cells which are connected to the first and second bit lines, a differential amplifier which is connected to one end of the first bit line and one end of the second bit line, a reference-current generating circuit which is connected to the other end of the second bit line and which generates a reference-current smaller than the cell current of the memory cells, and a dummy word line which is connected to the reference-current generating circuit, to activate the reference-current generating circuit in order to read data.

Semiconductor memory device of single-bit-line drive type

A basic unit block has a plurality of memory cells, a local bit line pair connected to the plurality of memory cells, and a bit line precharge circuit and a transfer gate switch circuit which are connected to the local bit line pair. The local bit line pairs in a plurality of basic unit blocks are connected to a global bit line pair via the transfer gate switch circuit. The global bit line pair constitutes a layered bit line structure together with the local bit line pair. The global bit line pair is laid out to extend in the same direction and is twisted once or more in this extending direction.

Semiconductor memory device having layered bit line structure

A semiconductor integrated circuit device is configured by eight transistors including the six transistors configuring the data holding section and the two NMOS transistors configuring the reading stage. The threshold voltage of the NMOS transistors configuring the reading stage is set low and the threshold voltage of the six transistors configuring the data holding section is set higher than the threshold voltage of the NMOS transistors configuring the reading stage. The cell current flowing from the bit line to the ground terminal can be set large and the large static noise margin (SNM) can be attained.

Semiconductor integrated circuit device having static random access memory mounted thereon

A semiconductor integrated circuit comprises a power supply voltage step down circuit and a MOS circuit group. The power supply voltage step down circuit is supplied with a power supply voltage and controlled by a standby control signal indicating an operating state or a standby state. The power supply voltage step down circuit outputs a first internal power supply voltage lower than the power supply voltage to an internal power supply line when the standby control signal indicates the operating state, and outputs a second internal power supply voltage lower than the first internal power supply voltage to the internal power supply line when the standby control signal indicates the standby state. The MOS circuit group including one or more MOS transistors which are supplied with the first or second internal power supply voltage from the internal power supply line to operate.

Voltage step down circuit with reduced leakage current

There is disclosed a phase detector and phase locked loop circuit in which a maximum operation frequency is high. The phase detector of the present invention comprises three S-R flip-flops each of which comprises two NAND gates, a NAND gate connected to an input terminal of the S-R flip-flop, and an inverter. Even when a phase difference between a reference clock signal and a clock signal is large, UP and DOWN signals can be outputted in accordance with the phase difference between both signals, and therefore the maximum operation frequency can be set to be higher than that of a conventional phase detector.

Phase detector and phase locked loop circuit

An SRAM cell comprising a first inverter comprising a first load element and a first driver NMOSFET, a second inverter comprising a second load element and a second driver NMOSFET and having input and output terminals cross-coupled to output and input terminals of the first inverter, respectively, a first transfer gate NMOSFET having a current path inserted between the first inverter and a first bit line and a gate connected to a word line, and a second transfer gate NMOSFET having a current path inserted between the second inverter and a second bit line and a gate connected to the word line, wherein a current drivability of the first inverter and the first transfer gate NMOSFET for the first bit line is set to be larger than that of the second inverter and the second transfer gate NMOSFET for the second bit line.

SRAM cell and integrated memory circuit using the same

A semiconductor device includes a plurality of diodes including a substrate of a first conductivity type biased to a reference potential, a well region of a second conductivity type formed in a surface region of the substrate, and a first diffusion region of the first conductivity type formed in a surface region of the well region, wherein the plurality of diodes have sizes of at least two kinds and are cascade-connected to each other.

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Kawasaki, Japan

Tomoaki Yabe