Renesas Electronics Corporation

Renesas Technology Corp.

Renesas Electronics America Inc.

Tomoaki Uno

Nobuyoshi Matsuura

Masaki Shiraishi

Yukihiro Sato

Yukihiro Satou

Hirokazu Kato

Katsuhiko Funatsu

Kazuyuki Umezu

Noboru Akiyama

Koji Tateno

Tetsuya Kawashima

Daisuke Kondo

Kisho Ashida

Toshio Nagasawa

Keiichi Okawa

Toru Ueguri

Yumi Kishita

Ryotaro Kudo

Tetsuo Sato

Koji Saikusa

Koujirou Matsui

Takehiko Sakamoto

Yoshito Nakazawa

Nobuyuki Shirai

Takayuki Iwasaki

Yuichi Yato

Yoshitaka Onaya

Hideo Numabe

Yasushi Takahashi

Kozo Sakamoto

Hideo Ishii

Yohihiro Satou

A plurality of unit MISFET elements connected in parallel with each other to make up a power MISFET are formed in an LDMOSFET forming region on a main surface of a semiconductor substrate. A control circuit that controls a gate voltage of the power MISFET is formed in a driver circuit region on the main surface of the semiconductor substrate. A wiring structure having a plurality of wiring layers made of the same metal material is formed on the semiconductor substrate. The gate electrodes of the plurality of unit MISFET elements formed in the LDMOSFET forming region are electrically connected to each other via gate wirings formed in all of the plurality of wiring layers made of the same metal material.

Semiconductor device

A semiconductor integrated circuit device includes a first voltage terminal, a second voltage terminal, an output terminal, a high-side MOSFET connected between the first voltage terminal and the output terminal, a low-side MOSFET connected between the output terminal and the second voltage terminal and having first and second gate electrodes, a drive circuit that complementally switches on and off the high-side MOSFET and low-side MOSFET, and a second gate electrode control circuit that generates a second gate control signal supplied to the second gate electrode of the low-side MOSFET. The second gate electrode control circuit has a voltage generating circuit that supplies a negative voltage negative in polarity relative to a voltage at the source of the low-side MOSFET, to the second gate electrode of the low-side MOSFET.

Semiconductor integrated circuit device and power supply system

In a non-insulated DC-DC converter having a circuit in which a power MOS&#x22c5;FET high-side switch and a power MOS&#x22c5;FET low-side switch are connected in series, the power MOS&#x22c5;FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS&#x22c5;FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS&#x22c5;FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Semiconductor device with first and second chips and connections thereof and a manufacturing method of the same

A control electrode GEis formed in a lower portion of a trench TRformed in a semiconductor substrate SUB, and a gate electrode GEis formed in an upper portion inside the trench TR. An insulating film Gis formed between the control electrode GEand a side wall and a bottom surface of the trench TR, an insulating film Gis formed between the side wall of the trench TRand the gate electrode GE, and an insulating film Gis formed between the control electrode GEand the gate electrode GE. A region adjacent to the trench TRincludes an n-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GEis not connected to a wiring connected to the gate electrode GE, and is not connected to a wiring connected to the n-type semiconductor region NR for a source.

A trench MOSFET is disclosed that includes a semiconductor substrate having a vertically oriented trench containing a gate. The trench MOSFET further includes a source, a drain, and a conductive element. The conductive element, like the gate is contained in the trench, and extends between the gate and a bottom of the trench. The conductive element is electrically isolated from the source, the gate, and the drain. When employed in a device such as a DC-DC converter, the trench MOSFET may reduce power losses and electrical and electromagnetic noise.

Trench MOSFET having an independent coupled element in a trench

In a non-insulated DC-DC converter having a circuit in which a power MOS&#x2022;FET high-side switch and a power MOS&#x2022;FET low-side switch are connected in series, the power MOS&#x2022;FET low-side switch and a Schottky barrier diode to be connected in parallel with the power MOS&#x2022;FET low-side switch are formed within one semiconductor chip. The formation region SDR of the Schottky barrier diode is disposed in the center in the shorter direction of the semiconductor chip, and on both sides thereof, the formation regions of the power MOS&#x2022;FET low-side switch are disposed. From the gate finger in the vicinity of both long sides on the main surface of the semiconductor chip toward the formation region SDR of the Schottky barrier diode, a plurality of gate fingers are disposed so as to interpose the formation region SDR between them.

Semiconductor device including Schottky barrier diode and power MOSFETs and a manufacturing method of the same

To improve the reliability in applying a tape to the rear surface of a substrate while securing the heat resistance of the tape applied to the rear surface of the substrate. There is a gap between a bottom surface of a ditch provided in a support member and an upper surface of a driver IC chip. On the other hand, the upper surface side of a lead frame is supported by the support member so that the bottom surface of the ditch contacts the upper surface of a Low-MOS clip mounted over a Low-MOS chip. Thus, even in a state where the driver IC chip and the Low-MOS chip are mounted on the upper surface side of the lead frame, the tape can be reliably applied to the rear surface of the lead frame (in particular, to the rear surface of the product region).

Method of manufacturing semiconductor device

The reliability of a semiconductor device is improved. A package of a semiconductor device internally includes a first semiconductor chip and a second semiconductor chip in which power MOS&#x2022;FETs are formed and a third semiconductor chip in which a control circuit controlling the first and second semiconductor chips is formed. The first to third semiconductor chips are mounted on die pads respectively. Source electrode bonding pads of the first semiconductor chip on a high side are electrically connected with a first die pad of the die pads via a metal plate. On a top surface of the die padD, a plated layer formed in a region where the second semiconductor chip is mounted, and another plated layer formed in a region where the metal plate is joined are provided and the plated layers are separated each other with a region where no plated layer is formed in between.

Semiconductor device having a chip mounting portion on which a separated plated layer is disposed

A semiconductor device is improved in reliability. A power MOSFET for switching, and a sense MOSFET for sensing a current flowing in the power MOSFET, which is smaller in area than the power MOSFET, are formed in one semiconductor chip. The semiconductor chip is mounted over a chip mounting portion, and sealed in a resin. To first and second source pads for outputting the current flowing in the power MOSFET, a metal plate is bonded. A third source pad for sensing the source voltage of the power MOSFET is at a position not overlapping the metal plate. A coupled portion between a source wire forming the third pad and another source wire forming the first and second pads is at a position overlapping the metal plate.

The present invention provides a non-insulated type DC-DC converter having a circuit in which a power MOS&#x2022;FET for a high side switch and a power MOS&#x2022;FET for a low side switch are connected in series. In the non-insulated type DC-DC converter, the power transistor for the high side switch, the power transistor for the low side switch, and driver circuits that drive these are respectively constituted by different semiconductor chips. The three semiconductor chips are accommodated in one package, and the semiconductor chip including the power transistor for the high side switch, and the semiconductor chip including the driver circuits are disposed so as to approach each other.

Semiconductor device including a DC-DC converter

Growing community of inventors

Takasaki, Japan

Tomoaki Uno