Kabushiki Kaisha Toshiba

Tomoaki Shino

Takashi Ohsawa

Takeshi Hamamoto

Takashi Yamada

Akihiro Nitayama

Hideaki Aochi

Ryo Fukuda

Tsuneaki Fuse

Shigeru Kawanaka

Kazumi Inoh

Makoto Yoshimi

Hideaki Nii

Sadayuki Yoshitomi

Yoshihiro Minami

Mamoru Terauchi

This disclosure concerns a memory comprising a semiconductor layer extending in a first direction; a source; a drain; a body between the source and the drain; a bit-line extending in the first direction; a first gate-dielectric on a first side-surface of the body; a first gate-electrode on the first side-surface of the body via the first gate dielectric film; a first gate line extending in the first direction, connected to a bottom of the first gate-electrode, and formed integratedly with the first gate-electrode using same material; a second gate dielectric on a second side-surface of the body; a second gate-electrode on the second side surface of the body via the second gate dielectric film; and a second gate line extending in a second direction crossing the first direction, connected to an upper portion of the second gate-electrode, and formed integratedly with the second gate-electrode using same material.

Semiconductor memory device and manufacturing method thereof

A semiconductor memory device includes bodies electrically floating; sources; drains; gate electrodes, each of which is adjacent to one side surface of the one of the bodies via a gate dielectric film; plates, each of which is adjacent to the other side surface of the one of the bodies via a plate dielectric film; first bit lines on the drains, the first bit lines including a semiconductor with a same conductivity type as that of the drains; and emitters on the semiconductor of the first bit lines, the emitters including a semiconductor with an opposite conductivity type to that of the semiconductor of the first bit lines, wherein the emitters are stacked above the bodies and the drains.

A memory includes a U-shape layer on a substrate; a first diffusion layer provided at an upper part of the U-shaped layer; a second diffusion layer provided at a lower part of the U-shaped layer; a body formed at an intermediate portion of the U-shaped layer between the first and the second diffusion layers; a first gate dielectric film provided on an outer side surface of the U-shaped layer; a first gate electrode provided on the first gate dielectric film; a second gate dielectric film provided on an inner side surface of the U-shaped layer; a second gate electrode provided on the second gate dielectric film; a bit line contact connecting the bit line to the first diffusion layer; a source line contact connecting the source line to the second diffusion layer, wherein cells adjacent in the first direction alternately share the bit line contact and the source line contact.

Semiconductor memory device

This disclosure concerns a semiconductor memory device comprising a semiconductor substrate; a first dielectric film provided on the semiconductor substrate; two Fins provided on the first dielectric film and made of a semiconductor material; a second dielectric film provided on facing inner side surfaces among side surfaces of the two Fins; a third dielectric film provided on outer side surfaces among side surfaces of the two Fins; a gate electrode provided via the second dielectric film between the inner side surfaces of the two Fins; and a plate electrode provided via the third dielectric film on the outer side surfaces of the two Fins, wherein the two Fins, the gate electrode, and the plate electrode are included in one memory cell.

Semiconductor memory device and method of manufacturing the same

A semiconductor memory device includes a supporting substrate including semiconductor materials. The memory device also includes an insulation film provided above the supporting substrate. The memory device further includes a first diffusion layer provided on the insulation film. In addition, the memory device includes a second diffusion layer provided on the insulation film. The memory device additionally includes a body region provided between the first diffusion layer and the second diffusion layer. The body region is in an electrically floating state and accumulates or releases electric charges for storing data. Also, the memory device includes a semiconductor layer penetrating the insulation film and electrically connecting the second diffusion layer to the supporting substrate to release electric charges from the second diffusion layer. Further, the memory device includes a gate insulation film provided on the body region. Additionally, the memory device includes a gate electrode provided on the gate insulation film.

The disclosure concerns a semiconductor memory device comprising a semiconductor layer; a charge trap film in contact with a first surface of the semiconductor layer; a gate insulating film in contact with a second surface of the semiconductor layer, the second surface being opposite to the first surface; a back gate electrode in contact with the charge trap film; a gate electrode in contact with the gate insulating film; a source and a drain formed in the semiconductor layer; and a body region provided between the drain and the source, the body region being in an electrically floating state, wherein a threshold voltage or a drain current of a memory cell including the source, the drain, and the gate electrode is adjusted by changing number of majority carriers accumulated in the body region and a quantity of charges trapped into the charge trap film.

The disclosure concerns a semiconductor memory device including an insulating film; a semiconductor layer provided on the insulating film; a source layer and a drain layer formed on the semiconductor layer; a body region provided between the source layer and the drain layer, the body region being in an electrically floating state, accumulating or emitting charges for storing data, and including a first body part and a second body part, the first body part being smaller than the second body part in a thickness measured in a direction perpendicular to a surface of the insulating film; a gate insulating film provided on the first body part and the second body part; and a gate electrode provided on the gate insulating film.

This disclosure concerns a memory comprising a charge trapping film; a gate insulating film; a back gate on the charge trapping film; a front gate on the gate insulating film; and a body region provided between a drain and a source, wherein the memory includes a first storage state for storing data depending on the number of majority carriers in the body region and a second storage state for storing data depending on the amount of charges in the charge trapping film, and the memory is shifted from the first storage state to the second storage state by converting the number of majority carriers in the body region into the amount of charges in the charge trapping film or from the second storage state to the first storage state by converting the amount of charges in the charge trapping film into the number of majority carriers in the body region.

A semiconductor memory device includes a semiconductor layer; a source layer provided in the semiconductor layer; a drain layer provided in the semiconductor layer; a body region provided in the semiconductor layer between the source layer and the drain layer; a gate insulation film provided on the body region; and a gate electrode provided on the gate insulation film, wherein data are written or read out by accumulating electric charge in the body region or releasing electric charge from the body region, and wherein a difference between the potential Vof the source layer in a data-retaining period and the potential Vof the gate electrode in the data-retaining period is smaller than a difference between the potential Vof the source layer in a data write period and the potential V.

Semiconductor memory device and method of driving a semiconductor memory device

A semiconductor memory device includes transistors, each including a first-conductivity-type semiconductor layer formed on a semiconductor substrate via a first insulating film, a second-conductivity-type source/drain regions formed in the semiconductor layer, a first-conductivity-type body region formed between the source region and the drain region in the semiconductor layer, the body region being electrically floating, and a gate electrode formed on a surface of a central portion of the body region via a second insulating film. In a section along a word line, which connects the gate electrodes together, a length of a boundary between the central portion of the body region and the second insulating film is smaller than a length of a boundary between the body region and the first insulating film. A second-conductivity-type counter impurity is doped in a surface portion of the central portion of the body region on which the second insulating film is formed.

Floating body-type DRAM cell with increased capacitance

A semiconductor device includes a semiconductor substrate; a first insulation layer formed on the semiconductor substrate; a semiconductor layer insulated from the semiconductor substrate by the insulation layer; a source region of a first conduction type and a drain region of the first conduction type formed in the semiconductor layer; a body region of a second conduction type formed in the semiconductor layer between the source region and the drain region, said body region being capable of storing data by accumulating or releasing electric charge; a second insulation layer formed on the body region; a word line formed on the second insulation layer and insulated from the body region by the second insulation layer; and a bit line electrically connected to the drain region, wherein the area of the body region in contact with the first insulation layer is larger than the area thereof in contact with the second insulation layer.

Floating body cell dynamic random access memory with optimized body geometry

A semiconductor memory device comprises a substrate; a first semiconductor layer of a first conduction type having a single crystalline structure isolated from the substrate by an insulator layer; a plurality of memory transistors, each having a gate electrode connected to a word line, a pair of impurity regions of a second conduction type serving as a drain region and a source region formed in the first semiconductor layer, and a channel body of the first conduction type formed in the first semiconductor layer between the impurity regions, and operative to store data as a state of majority carriers accumulated in the channel body; a plurality of device isolation regions formed to isolate memory transistors having gate electrodes commonly connected to the same word line from each other among the plurality of memory transistors; and a plurality of impurity region isolation regions formed to isolate adjacent drain regions from each other and adjacent source regions from each other, the impurity region isolation region having a smaller width than that of the device isolation region.

Semiconductor memory device for storing data as state of majority carriers accumulated in channel body and method of manufacturing the same

A semiconductor device includes a substrate, a semiconductor layer of a first conductivity type having a single-crystal structure, and a plurality of transistors each including a first gate electrode provided above the semiconductor layer with a first gate insulation film laid therebetween, a pair of impurity regions of a second conductivity type being provided in the semiconductor layer and each becoming a source or drain region, and a channel body of the first conductivity type provided in the semiconductor layer at a portion between these impurity regions. The device also includes a first gate line for common connection of the first gate electrodes of the transistors, a dielectric layer provided above the substrate in an extension direction of the first gate line, for supporting the semiconductor layer under the pair of impurity regions to thereby dielectrically isolate between the substrate and the semiconductor layer, a second gate electrode provided above the substrate in such a manner as to underlie the channel bodies of the transistors and oppose the channel bodies with a second gate insulation film laid therebetween, the second gate electrode having a gate length larger than a onefold value of a gate length of the first gate electrode and yet less than or equal to thrice the gate length, and a second gate line provided above the substrate along the extension direction of the first gate line while being placed between portions of the dielectric layer underlying the pair of impurity regions, the second gate line being for common connection of the second gate electrode.

Semiconductor device including transistors formed in semiconductor layer having single-crystal structure isolated from substrate

First and second MOS transistors are formed in first and second active areas, respectively, and their gates are configured from a first gate electrode in the first and second transistors. Third and fourth MOS transistors are formed in the second and a third active areas, respectively, and their gates are configured from second and third gate electrodes in the third and fourth transistors. Fifth and sixth MOS transistors are formed in a fourth active area, and their gates are configured from the third and fourth gate electrodes in the fifth and sixth transistors. An end portion of the first gate electrode projecting from the first active area is obliquely arranged relative to a gate width direction of the first transistor, and an end portion of the third gate electrode projecting from the third active area is obliquely arranged relative to a gate width direction of the fourth transistor.

Semiconductor device formed in semiconductor layer on insulating film

A semiconductor device includes a semiconductor layer of a first conductive type formed in an active region, a first gate electrode formed on the semiconductor layer via a gate insulating film in a predetermined pattern, a first insulating mask formed on at least a part of the first gate electrode and a part of the semiconductor layer, and a pair of first diffusion regions of a second conductive type formed in the active region not covered with the first insulating mask and first gate electrode. The pair of first diffusion regions is positioned adjacent to the first gate electrode and being used as a source and drain.

Growing community of inventors

Kawasaki, Japan

Tomoaki Shino