Ricoh Company, Ltd.

Tomoaki Ozaki

Shinichi Yamaura

A SIMD microprocessor, which can be included in an image processing apparatus using an image processing method used therein, includes a global processor and multiple processor elements controlled by the global processor. Each single processor element of the multiple processor elements includes multiple operation units. The global processor is configured to control the multiple processing elements to uniformly change a configuration of the multiple operation units in the single processor element to determine a number of data units of operation according to the multiple operation units either operated individually or in cooperation with each other in the single processor element and a width of data processed per data unit of operation performed in the single processor element. A processor element number is assigned per data unit of operation to the single processor element to use for executing an operation.

SIMD microprocessor, image processing apparatus including same, and image processing method used therein

A disclosed image processing apparatus includes a SIMD microprocessor in which multiple processor elements are arranged in one dimension, each of the processor elements including multiple access registers arranged in stages for storing image data; and multiple data processing devices corresponding one-to-one with the stages of the access registers, arranged in one dimension in the same direction as the processor elements, and configured to read and write image data from/to the access registers. The access registers of each of the stages, each of which access registers is included in a different one of the processor elements, are connected with a common line. Wiring outlets, each of which connects the common line of a different one of the stages to a corresponding data processing device, are individually disposed within the SIMD microprocessor in such a manner that each wiring outlet has a shortest possible distance to the corresponding data processing device.

SIMD image forming apparatus for minimizing wiring distance between registers and processing devices

A method of labeling of image data includes reading the image data sequentially with units of two successive pixels and providing one label to a target unit of two successive pixels in the image data when a preliminary label is to be assigned to at least one of the two successive pixels of the target unit. And an image processing apparatus includes a memory configured to store image data, a processor configured to process the image data with units of two successive pixels and to provide one label to a target unit of two successive pixels when a preliminary label is to be assigned to at least one of the two successive pixels of the target unit and a memory controller arranged between the memory and the processor and configured to control reading and writing the image data.

Image processing apparatus and method of image processing capable of effective labeling

An image processing apparatus includes a plurality of processor elements including registers and configured to process respective data items, a global processor configured to control the plurality oaf processor elements; the global processor and the plurality of processor elements constituting an SIMD microprocessor, and a data control device coupled to a data transfer port for accessing the registers, the processor elements configured to perform a contiguity check and tentative labeling of pixels adjacent in a sub-scan direction as parallel processes with respect to binary image data, the data control device configured to perform a contiguity check and tentative labeling of pixels adjacent in a main scan direction as consecutive processes, and the parallel processes performed ahead of the consecutive processes with respect to a line of interest in the binary image data.

Image processing apparatus with SIMD-type microprocessor to perform labeling

An image processing apparatus includes a plurality of processor elements including registers and configured to process respective data items, a global processor configured to control the plurality of processor elements; the global processor and the plurality of processor elements constituting an SIMD microprocessor, and a data control device coupled to a data transfer port for accessing the registers, the processor elements configured to perform a contiguity check and tentative labeling of pixels adjacent in a sub-scan direction as parallel processes with respect to binary image data, the data control device configured to perform a contiguity check and tentative labeling of pixels adjacent in a main scan direction as consecutive processes, and the parallel processes performed ahead of the consecutive processes with respect to a line of interest in the binary image data.

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Hyogo, Japan

Tomoaki Ozaki