Kawasaki Microelectronics, Inc.

Tomoaki Nimura

Ryuji Ariyoshi

Isamu Kuno

Hiroyasu Kunitomo

A semiconductor integrated circuit that includes a circuit element with a reduced parasitic capacitance and has a short start-up time. A well of the different type of conduction from that of the substrate is formed in the area of the surface of the semiconductor substrate under the circuit element. A constant voltage, which biases the junction between the well and the semiconductor substrate in a reverse direction, is applied to the well through a resistor having a higher impedance compared with the impedance of the capacitance of the reverse-biased junction between the well and the substrate at the frequency of the signal applied to the circuit element.

Growing community of inventors

Chiba, Japan

Tomoaki Nimura