Matsushita Electric Works, Ltd.

Industrial Technology Research Institute

Panasonic Electric Works Co., Ltd.

Tomoaki Nemoto

Tzong-Ming Lee

Shu-Chen Huang

Kai-Chi Chen

Hsun-Tien Li

Taro Fukui

Shinji Hashimoto

Hideo Nakanishi

Hiroyuki Yagyu

Tomoaki Matsushima

Tooru Nakashiba

Yuuki Kasai

Kouhei Kotera

Yukio Matsushita

A material for an optical circuit-electrical circuit mixedly mounting substrate comprises a light permeable resin layer, and an optical circuit forming layer that is made of a light permeable resin of which refractive index increases (or decreases) when irradiated with an activating energy beam and is disposed adjacent to the light permeable resin layer, wherein a refractive index of a portion of the optical circuit forming layer is higher (or lower) than that of the light permeable resin layer when the material for the optical circuit-electrical circuit mixedly mounting substrate is irradiated with an activating energy beam so that said portion is irradiated.

Material for substrate mounting optical circuit-electrical circuit mixedly and substrate mounting optical circuit-electrical circuit mixedly

A material for an optical circuit-electrical circuit mixedly mounting substrate comprises a light permeable resin layer, and an optical circuit forming layer that is made of a light permeable resin of which refractive index increases (or decreases) when irradiated with an activating energy beam and is disposed adjacent to the light permeable resin layer,

Material for substrate mounting optical circuit-electric circuit mixedly and substrate mounting optical circuit-electric circuit mixedly

A chip package structure and a process for fabricating the same is disclosed. The chip package structure mainly comprises a carrier, a chip and an encapsulating material layer. To fabricate the chip package, a carrier and a plurality of chips are provided. Each chip has at least an active surface with a plurality of bumps thereon. The chips and the carrier are electrically connected. An encapsulating material layer that fills the bonding gap between the chips and the carriers and covers the chips and carrier is formed. The encapsulating material layer between the chips and the carrier has a first thickness and the encapsulating material layer over the chips has a second thickness. The second thickness has a value between half to twice the first thickness.

Chip package structure and process for fabricating the same

A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is flip-chip bonded and electrically connected to the carrier or another chip. There is a flip-chip bonding gap between the chip and the carrier or other chips. A heat sink is positioned on the uppermost chip. The encapsulating material layer fills the flip-chip bonding gap as well as a gap between the uppermost chip and the heat sink. A part of the surface of the heat sink away from the upper-most chip is exposed. Furthermore, the encapsulating material layer is formed in a simultaneous molding process. For example, the chip is separated from the heat sink by a distance between 0.03&#x2dc;0.2 mm, and the encapsulating material has a thermal conductivity greater than 1.2 W/m.K.

Chip package structure

A chip package structure is disclosed. The chip package structure essentially comprises a carrier, one or more chips, a heat sink and an encapsulating material layer. At least one of the chips is bonded and electrically connected to the carrier or another chip using a flip-chip bonding technique. A flip-chip bonding gap is set up between the chip and he carrier or other chips. The heat sink is set up over the top chip. The heat sink has an area bigger than the chip. The encapsulating material layer fills up the flip-chip bonding gap and covers the carrier as well as the heat sink. The encapsulating material layer is formed in a simultaneous molding process and has a thermal conductivity more than 1.2 W/m.K. Furthermore, a plurality of standoff components may be selectively positioned on the heat sink.

Growing community of inventors

Osaka, Japan

Tomoaki Nemoto