Sharp Kabushiki Kaisha Corporation

Sharp Kabushiki Kaishi

Tomoaki Nakao

Hiroaki Fujino

Shigeki Tamai

Yukihiro Shimizu

Michihiro Nakahara

Takahiro Nakai

Tetsuya Minamiguchi

In one embodiment of the present invention, an operational amplifier circuit, a switching element is closed and a switching element is opened. A latch circuit DL latches an output voltage of an operational amplifier and supplies a Q output corresponding to the output voltage. A control circuit supplies an offset adjustment signal to an offset adjustment input terminal OR of the operational amplifier, thereby adjusting an offset of the output voltage. The latch circuit DL latches again the output voltage thus adjusted and minutely adjusts the offset adjustment signal so as to adjust the remaining offset. Weighting is carried out in accordance with how many times latching has been carried out, and the offset of the output voltage of the operational amplifier is quantized, thereby obtaining a binary logical signal and storing the signal in the control circuit.

Offset adjustment device, semiconductor device, display device, offset adjustment method, noise detection device, and noise detection method

The present invention provides an offset adjusting circuit and an operational amplifier circuit. In the operational amplifier circuit (), a switching element (S) is closed and a switching element (S) is opened. The latch circuit DL latches an output voltage of an operational amplifier (), and output a Q-output in accordance with the output voltage. The control circuit () inputs an offset adjustment signal sto an offset adjustment input terminal OR of the operational amplifier (). Then, the latch circuit DL latches the output voltage having been subjected to the offset adjustment, and the offset adjustment signal sis finely adjusted for adjusting the remaining offset. In this way, the offset in the output voltage of the operational amplifier () is quantized in accordance with the number of times the latching operation has been performed, and is stored in the control circuit () in the form of a binary logical signal.

Offset adjusting circuit and operational amplifier circuit

A P-channel MOS transistor and an N-channel MOS transistor are respectively controlled by a first control signal and a second control signal. The first control signal CTLand the second control signal CTLare independent from each other. The second control signal CTLis generated by a NOR circuitto which a data signal DATA and a third control signal CTLare inputted. A load capacitor Cwhich samples the first electric potential or the GND electric potential is configured by a gate capacitance of another MOS transistor.

Level shifting circuit and display element driving circuit using same

Reference voltage generation means is constituted by including first voltage division means constituted so as to be able to generate a plurality of levels of gradation display voltages by resistance-dividing voltage differences between a plurality of reference voltages VR by a plurality of dividing resistors connected in series, second voltage division means constituted so as to be able to generate some or all of the gradation display voltages by resistance-dividing voltage differences between a plurality of reference voltages VR by a plurality of auxiliary resistors connected in series, and switching means for mutually connecting all or a part of the plurality of gradation display voltages generated by the first voltage division means and the second voltage division means. The switching means is turned on during the transient state period in which the DA conversion circuit responds and the first and second voltage division means operate.

Liquid-crystal driver and liquid-crystal display

A DA converter is for converting N-bit digital signals to 2 analog signals, and includes a reference voltage generating circuit for generating the reference voltages having 2 &plus;1 voltage levels, a reference voltage selector circuit for selecting two reference voltages having adjacent voltage levels according to the A bits of a digital signal, an output voltage selector circuit for selecting one interpolation voltage from 2 &minus;1 interpolation voltages predetermined between the voltage levels of the two reference voltages in accordance with the N-A bits of the digital signal, and a voltage follower circuit for producing the above interpolation voltage by linear interpolation based on the two reference voltages. With this structure, in a DA converter and a liquid crystal driving device incorporating the DA converter, despite a possible increase in the number of voltages required for a display with more gradation levels, large increases in the number of circuit composing elements can be avoided, thus preventing an increase in manufacturing cost and permitting the production of more compact devices.

DA converter and liquid crystal driving device incorporating the same

There is provided a gray scale display reference voltage generating circuit that can change a gamma correction characteristic in accordance with a liquid crystal material and LCD panel characteristics. Resistor elements R through R have a resistance ratio for gamma correction and generate gamma-corrected intermediate voltages on the basis of voltages across both input terminals V and V A gamma correction adjustment circuit adjusts the gamma-corrected intermediate voltages upward or downward on the basis of adjustment data latched in a data latch circuit By thus supplying the adjustment data corresponding to the liquid crystal material and the LCD panel characteristics to the data latch circuit the gamma correction characteristic can be changed in accordance with the liquid crystal material and the LCD panel characteristics without modifying the design of a source driver.

Gray scale display reference voltage generating circuit capable of changing gamma correction characteristic and LCD drive unit employing the same

A standard voltage generating circuit produces 2 &plus;1 mutually different standard voltages. A selector circuit stores standard voltage pairs so that each of the digital signals corresponds to one of the standard voltage pairs. No standard voltage pairs produce the same mean value. Upon reception of an input digital signal, the selector circuit selects one of the standard voltage pairs which corresponds to the input digital signal and provides the standard voltages of the selected pair for output. The standard voltages provided for output by the selector circuit are supplied to a voltage follower circuit which provides an output voltage having a mean value of the input standard voltages. In a DA converter and a liquid crystal driving device incorporating the DA converter, despite a possible increase in the number of voltages required for a display of more colors and more half-tones, large increases in the number of circuit arrangement elements can be avoided and increases in manufacturing cost can be restrained, allowing the device to be built in a more compact size.

An incidental offset voltage caused by discrepancies in material and workmanship can be averaged by (1) using two input transistors of a differential amplifier alternately, and (2) switching output signals from both the input transistors through two switches provided to an output end. Consequently, a downsized, less-power-consuming, highly-reliable differential amplifier which is insensitive to an incidental offset voltage caused by discrepancies in material and workmanship can be provided. Also, by employing such a differential amplifier, a less-power-consuming and highly reliable operational amplifier and a liquid crystal driving circuit capable of showing display of an upgraded quality can be realized.

Differential amplifier, operational amplifier employing the same, and liquid crystal driving circuit incorporating the operational amplifier

A liquid crystal driving circuit includes: a charge capacitor and a distribution capacitor, each having a first electrode and a second electrode, respective first electrodes of the charge capacitor and the distribution capacitor being connected to each other; a first switch for connecting and disconnecting respective second electrodes of the charge capacitor and the distribution capacitor; a select switch for selecting application of a first reference voltage and a second reference voltage with respect to the second electrode of the charge capacitor by connection or disconnection; an operational amplifier for outputting an analog signal for multi-tone display in accordance with an amount of charge of the distribution capacitor and the second reference voltage; and a controller for alternately controlling the first switch and the select switch in accordance with a digital signal for multi-tone display.

Liquid crystal driving circuit

A reference voltage having a plurality of voltage levels which increase stepwise over time is supplied to source lines on a display panel through a plurality of analog switches. A value representing a number of gradation display data levels for the source lines during a horizontal scanning period is supplied as one input in to a comparison circuit. A count registered by a counter and representing a gradation clock signal is supplied as a second input. Where the count is less than the value, the analog switches remain conducted. Once the count equals to or exceeds the value, the analog switches are cut off, thus enabling the supplied reference voltage to be applied as a driving voltage to a pair of pixel electrodes. The driving voltage corresponds to the number of gradation display data levels and is held constant at the pixel electrodes for the remaining horizontal scanning period.

Method and apparatus for driving display panel

An operational amplifier circuit 21 comprises transistors N14, N15 in a first output amplifier circuit 24, and transistors P24, P25 in a second output amplifier circuit 25. When a second differential amplifier circuit 23 is cut off, the output is driven by transistor P13 and transistors N14, N15. When a first differential amplifier circuit 22 is cut off, the output is driven by transistor N23 and transistors P24, P25. Therefore, if such a voltage as to cut off one differential amplifier circuit is given from opposite phase and in-phase input terminals 31, 32, the output can be produced. In such constitution, without using depletion type transistors that require particular manufacturing process, the range of the voltage that can be entered in the input terminal can be extended.

Operational amplifier circuit with an extended input voltage range

When a transistor 1 is turned off, and transistors 5 and 7 are both turned on, first and second output signals Oa and Ob both attain a first potential GND irrespective of the logic level of a second logic signal Ib and a third logic signal /Ib. When the transistor 1 is turned on and the transistors 5 and 7 are both turned off by the first logic signal Ia, a transistor 4 is turned off and a transistor 6 is turned on, whereby first and second output signals Oa and Ob attain a second potential VEE and the first potential GND, respectively. When the transistor 1 is turned on, and transistors 5 and 7 are turned off, the transistor 4 is turned on and the transistor 6 is turned off, whereby the first and second output signals Oa and Ob attain the first potential GND and the second potential VEE, respectively. Thus a composite logic circuit can be implemented with 7 transistors.

Composite logic circuit

A logic circuit for outputting signals corresponding to an input signal depending on a clock signal sent from an external source includes at least one synchronous flip-flop being synchronized with the clock signal, so that the flip-flop latches the input signal, and a unit for controlling an input of the clock signal to the flip-flop based on a difference between logic levels of an output signal of the flip-flop and an input signal newly latched by the flip-flop.

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Yamatokoriyama, Japan

Tomoaki Nakao