Hitachi, Ltd.

Hitachi Process Computer Engineering, Inc.

Other

Tomoaki Nakamura

Shigenori Kaneko

Masahiko Saito

Hiroshi Ohno

Takeshi Miyao

Manabu Araoka

Ryokichi Yoshizawa

Takanori Yokoyama

Kunihiko Tsunedomi

Masaru Shimada

Saburou Iijima

Nobuyasu Kanekawa

Masayuki Sakata

Yoshiaki Takahashi

Toshiaki Arai

Tomoki Sekiguchi

Yoshiki Kobayashi

Yoshihiro Miyazaki

Tadashi Kamiwaki

Hiroaki Fukumaru

Masayuki Tanji

Koji Masui

Manabu Yamauchi

Shinichiro Kanekawa

Katsunori Tagiri

Naoshi Kato

Atsushi Shikama

Kinji Mori

Yoshinori Endo

Kozo Nakamura

Katsumi Kawano

Masayuki Orimo

Keiichi Nakane

Shigeki Hirasawa

Hitoshi Suzuki

Koji Hirai

Taro Inoue

Hiroshi Fujise

Hiroaki Nakanishi

Hiroshi Wataya

Naoki Miwa

Hiroshi Nosaki

Yasuo Sekine

Hidebumi Miyata

A computer system having a plurality of operating systems and a module for switching the operating systems in view of priorities of tasks to be performed by each of the operating systems. Each of the operating systems performing a plurality of processes or threads in accordance with the priorities assigned to these processes or threads has a module for notifying the computer system of the priority of the currently executing process or thread. The computer system includes a module for translating the priorities sent from each operating system into priorities (normalized priorities) common-throughout the computer system, and a module for comparing the normalized priorities obtained by the priority translation module in order to select and execute preferentially the operating system having a common priority higher than that of any other operating system.

Computer executing multiple operating systems

A distributed computing system having a plurality of computers different from each other in performance, load, and type, uniformly manages local priority schemes adapted in the respective computers by utilizing the concept of 'urgency' or 'time limit'. Each of the computers includes a priority level conversion procedure for performing a conversion between an urgency level and a priority level of processing in accordance with the performance and the load of the computer, and a priority level changing procedure for changing a priority level of a program, which executes the processing, in accordance with a priority level indicated by the priority level conversion procedure.

Distributed computing system

An inter-OS control software for switching OS's in operation executed on a single CPU is installed, and plural OS's are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.

Multiple operating system control method

A computer system is provided with a scheme to making the input and output device provided in a computer in common for a plurality of operating system, in a multiple operating system control unit operating a plurality of mutually distinct operating systems on one computer system. The computer system includes a plurality of operating systems, and OS switching unit for switching a plurality of operating systems. The OS switching means makes reference to a preferential interrupt table on the basis of an interrupt factor for switching to corresponding operating system and calls interrupt processing means incorporated in the operating system.

Computer system with multiple operating system operation

A distributed computing system --,--; having a plurality of computers that differ from each other in terms of performance, load, and type, uniformly manages local priority schemes adapted in the respective computers by utilizing the concept of &ldquo;urgency&rdquo; or &ldquo;time limit&rdquo;. Each of the computers includes a priority level conversion procedure for performing a conversion between an urgency level and a priority level of processing in accordance with the performance and the load of the computer, and a priority level changing procedure for changing a priority level of a program, which executes the processing, in accordance with a priority level indicated by the priority level conversion procedure.

A computer system has a plurality of processing units (,-,-,-n) connected via one or more system buses (,-,-,). Each processing unit (,-,-,-n) has three or more processors (,-,-,-,) on a common support board (PL) and controlled by a common clock unit (,). The three processors (,-,-,-,) perform the same operation and a fault in a processor (,-,-,-,) is detected by comparison of the operations of the three processors (,-,-,-,). If one processor (,-,-,-,) fails, the operation can continue in the other two processors (,-,-,-,) of the processing unit (,-,-,-n), at least temporarily, before replacement of the entire processing unit (,-,-,-n). Furthermore, the processing unit (,-,-,-n) may have a plurality of clocks (A,B) within the clock unit (,), with a switching arrangement so that the processors (,-,-,-n) normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories (,) may be connected in common to the processors (,-,-,-,), so that failure of one cache memory (,) permits the processing unit (,-,-,-n) to continue to operate using the other cache memory (,). Coherence of the contents of the cache memories (,) may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory (,-,-,-,) of a processor (,-,-,-,) which differs from that in the external cache memory (,). Coherence of protocols may also ensure that data in caches (,) of the different processor units (,-,-,-n) are always correct.

Processing unit for a computer and a computer system incorporating such a processing unit

A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board (PL) and controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit, at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks (A,B) within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock (A), but receive pulses from an auxiliary clock (B) if the main clock (A) fails. Switching between the main and auxiliary clock (A,B) involves comparison of the pulse duration from the clocks (A,B). Additionally, a plurality of cache memories may be connected in common to the processors, so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.

Processing unit for a computer and a computer system incorporating such

A distributed computing system, having a plurality of computers that differ from each other in terms of performance, load, and type, uniformly manages local priority schemes adapted in the respective computers by utilizing the concept of 'urgency' or 'time limit'. Each of the computers includes a priority level conversion procedure for performing a conversion between an urgency level and a priority level of processing in accordance with the performance and the load of the computer, and a priority level changing procedure for changing a priority level of a program, which executes the processing, in accordance with a priority level indicated by the priority level conversion procedure.

A computer system and method for enabling memory expansion without shutting off the computer system are disclosed. The computer system has a dual memory configuration and supports memory insertion and extraction while being on-line. The memory content of one system may be copied to the memory of another system according to a predetermined priority or after a predetermined delay. Memory may be used efficiently during the insertion or extraction by securing a status management table expansion area in an expanded portion of memory. Memory may be expanded in computer systems that do not have an open memory slot by replacing the installed memory with a memory having a larger capacity.

Computer system including a dual memory configuration which supports

A method for executing programs in a distributed processing system includes executing in a plurality of first processors different programs which perform the same function. Messages, containing data representing execution result output from said different programs and attribute information indicating function to be performed by the different programs, are transmitted from the first processors to a network. A second processor then receives these messages and selects a message therefrom based on an analysis of the attribute information contained in all of the received messages. The second processor then executes an application program using the data contained in the selected message. Alternatively, the message-selecting step is made based on both the attribute information and data contained in the messages received in the second processor. Each of the messages from the first processors may include graphic image data which can be analyzed and shown on a display.

Multiple-execution method of multiple-version programs and computer

A main memory managing arrangement involves allotting a request program to one of three distinct areas of main memory by looking in an area managing table which stores head addresses and the capacities of the respective areas. The areas allocated in main memory correspond to a single OS area, a single first class program area and a single second class program area. An empty page managing table is also provided for indicating the presence or absence of an empty area conformable to a request in an allocated area. A request program is allocated to the allocated area when the presence of the empty area of required capacity is determined. The memory capacity for a resident program can be assured independently of the memory capacities for other programs to enhance reliability conformable to real-time process computers.

Main memory managing method and apparatus in which main memory is

The present invention provides a non-stop data processing system having an online data backup function. The method according to the present invention is a data backup method for a computer system having a central processing unit for performing multitask processing, a multiple memory constituted by a plurality of memory devices for online storing data processed by tasks of the central processing unit, and a data backup memory for saving data of the multiple memory, wherein the central processing unit performs parallel processing of (a) user task(s) to treat usual work between the central processing unit and the multiple memory and a maintenance task to save data online from memory devices as a part of the multiple memory to the data backup memory. A data processing system according to the present invention is a data processing system having a central processing unit for performing multitask processing, a multiple memory constituted by a plurality of memory devices for storing data currently processed, and a data backup memory for saving data of the multiple memory, wherein: the central processing unit has (a) user task(s) to write currently processed data into the multiple memory, and a maintenance task to stop updating of memory devices as a part of the multiple memory and save data to the data backup memory; and the system further has an online interface whereby access to the respective memory devices of the multiple memory by the user task(s) and the maintenance task is relayed online.

Data backup method and data processing system having data maintenance

In a data processing device, when exchanging a plug-in package with another without breaking the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.

Data processing device and plug-in package

In a data processing device, when exchanging a plug-in package with another without breaking off the power to be supplied to the data processing device, a package removing lever is equipped with a locking piece. The lever does not move and the package hence cannot be removed, until the locking piece is released. In response to the release operation of the locking piece, a switch is activated to break off the power supply for the package. After the package is mounted perfectly, the power for the package is switched on by the action of the locking piece, thus preventing any misoperation when removing the package.

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Katsuta, Japan

Tomoaki Nakamura