Nippon Telegraph and Telephone Corporation

Tomoaki Kawamura

Shoko Oteru

Saki Hatta

Kenji Kawai

Nobuyuki Tanaka

Shoko Ohteru

Satoshi Shigematsu

Shuhei Yoshida

Koji Yamazaki

Yuta Ukon

Junichi Kato

Hiroyuki Uzawa

Naoki Miura

Yuki Arikawa

Takahiro Hatano

Namiko Ikeda

Ritsu Kusaba

Takeshi Sakamoto

Eiji Oki

Jun Terada

Naoaki Yamanaka

Koyo Nitta

Masami Urano

Mamoru Nakanishi

Kazuhiko Terada

Yusuke Ohtomo

Kazuyoshi Nishimura

Keiji Kishine

Tsuneo Matsumura

Minoru Togashi

A packet processing apparatus includes a packet processor that performs processing on a packet received from a communication line and outputs data that is a result of the processing, a data combiner that concatenates a plurality of pieces of data output from the packet processor to generate a data block, and a combination data transferor that DMA-transfers the data block generated by the data combiner to a data memory. The combination data transferor writes information on an address in the data memory of a beginning of an individual piece of data in the data block to a descriptor that is a data area on a predetermined memory.

Packet processing device and packet processing method

The packet processing apparatus includes a packet memory, a transmission processing unit that writes a plurality of packets to be transmitted to the packet memory to generate a combination packet into which the plurality of packets have been concatenated, a line handling unit that sends packets to a communication line, and a combination packet transfer unit that DMA-transfers the combination packet from the packet memory to the line handling unit. The transmission processing unit writes information on an address in the packet memory of beginning data of an individual packet in the combination packet to a descriptor. The line handling unit separates the DMA-transferred combination packet into a plurality of packets and sends the plurality of packets to the communication line.

In a recording device, a data memory including a DRAM having a write pointer for each of banks, and a queue control memory that stores an active flag is provided. When frame data is written into a write-target queue, a bank for which an active flag indicates an activated state is selected as a write-target bank among the banks to write the frame data, and if there is no bank for which an active flag indicates an activated state, a bank for which an active flag indicates a deactivated state is selected as a write-target bank, a row address of a write pointer of the bank is activated, and thereafter the frame data is written.

Communication input-output device

A network load balancing apparatus has a data buffer for each communication path of a received packet's transfer destinations, calculates a first hash value using a field value contained in the packet, determines, based on the field value of the packet or the first hash value, a communication path of a transfer destination of the packet subject to external transfer control for transmission to a predetermined external server, determines, based on the first hash value, a communication path of a transfer destination of the packet to be subject to priority control, determines, based on a second hash value based on the first hash value, a communication path of a transfer destination of the packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, and transmits the packet to a data buffer corresponding to the communication path of the transfer destination.

Network load dispersion device and method

A network load balancing apparatus has a data buffer provided to each communication path of transfer destinations of a received packet and being associated with a virtual function, determines a destination virtual function based on a field value of the received packet, determines a communication path of a transfer destination of a packet to be subject to priority control based on a first hash value calculated using the field value, determines a communication path of a transfer destination of a packet to be subject to load balancing control, to match a preset load balancing situation of the data buffer, based on a second hash value based on the first hash value, and transmits the packet to a data buffer corresponding to the destination virtual function and the communication path of the transfer destination.

Network load distribution device and method

A packet processing apparatus includes a line adapter configured to receive packets from a communication line, a packet combining unit configured to generate a combined packet by combining a plurality of packets received from the communication line, a packet memory configured to store packets received from the communication line, and a combined packet transferring unit configured to DMA transfer the combined packet generated by the packet combining unit to the packet memory. The combined packet transferring unit determines an address of start data of each packet inside the combined packet on the packet memory, writes information on the address into the descriptor that is a predetermined data area on a memory, and DMA transfers the combined packet to the packet memory.

An OLT () is provided with a priority control bypass circuit () and an encryption/decryption bypass circuit (), or an ONU () is provided with a priority control bypass circuit () and an encryption/decryption bypass circuit (), and one or both of encryption/decryption processing and priority control processing are bypassed in accordance with a priority control bypass instruction (BP) and an encryption/decryption bypass instruction (BE), which are set in advance. This reduces a processing delay that occurs in the OLT or the ONU.

PON system, wireless network system, data transfer method, OLT, and ONU

An upstream allocation circuit () and a downstream allocation circuit () are provided in an OLT (). For example, a superimposed frame obtained by bundling upstream frames (upstream control frames+upstream data frames) from all ONUS is input to the upstream allocation circuit () via a frame reproduction circuit (-). The superimposed frame may be generated at the stage of optical signals or generated after converting optical signals into electrical signals. The upstream allocation circuit () allocates each of the upstream control frames bundled into the superimposed frame to a predetermined PON control circuit () based on information (PON port number or LLID) added to the frames. The downstream allocation circuit () allocates, to a preset frame reproduction circuit (), each downstream control frames output from the PON control circuits ().

Station-side apparatus in optical transmission system and optical transmission system

A selection and distribution circuit () is provided between N optical transceivers () and one PON control circuit (). The selection and distribution circuit () selects the optical transceiver () corresponding to an upstream frame that time-divisionally arrives, thereby transferring the upstream frame opto-electrically converted by the transceiver () to the PON control circuit () and distributing a downstream frame from the PON control circuit () to each optical transceiver (). A power supply control circuit () stops power supply to at least one of one of optical transceivers () that are not used to transfer the frame of the optical transceivers () and a circuit that is not used to transfer the frame in the selection and distribution circuit (). This can reduce the system cost per ONU in the optical transmission system.

Station-side device and optical transmission system

An OLT () is formed by N optical transceivers (), one PON control circuit (), and one selection and distribution circuit (). An optical transceiver selection control signal (SC) is transferred from the PON control circuit () to the selection and distribution circuit (). The optical transceiver selection control signal (SC) indicates the timing of a discovery window, the timing of a grant, and a logical link identification number of a registered ONU assigned to the grant (a logical link identification number for a logical link with the registered ONU). The selection and distribution circuit () selects one optical transceiver (-(s is an integer falling within a range of 0 to N&#x2212;1)) from the optical transceivers (-to-N) based on the optical transceiver selection control signal (SC) from the PON control circuit ().

Station-side apparatus in optical transmission system, optical transmission system, and optical transmission method

Identifier information (LLID) of an ONU and transfer instruction information indicating a transmission system as the output destination of a downstream frame are registered in a table () in correspondence with each of the destination IDs of the ONUs or user apparatuses connected to the ONUs. Upon receiving a downstream frame from a host apparatus, a frame transfer processing unit () acquires an LLID and transfer instruction information corresponding to the destination ID of the downstream frame from the table ().

Station-side apparatus and frame transfer apparatus

In a control frame processing unit (), the number of control frames from a frame demultiplexing unit () is counted for each of LLIDs given to the control frames. If the number of frames during a predetermined count period is equal to or smaller than a preset threshold, some or all of the control frames are written in a storage device () as processing data. When the number of frames has exceeded the threshold, writing data of the control frames having the LLID in the storage device is stopped. Hence, even when the number of control frames from ONUs increases, software processing can be executed properly.

OLT and frame transfer control method

A recovered clock () is generated by making the phase of a reference clock () having the same frequency as the data rate frequency of input data () match the phase of the input data (). The input data () is written in a FIFO () using the recovered clock (). For readout from the FIFO (), the FIFO () is caused to output recovered data () using the reference clock () asynchronous to the recovered clock ().

CDR circuit

A contention control circuit which temporarily stores cells arriving from a respective plurality of input lines to output cells to a single output line without collisions. The contention control circuit compares, at each input line in turn, the priority of the cell that has arrived from that input line, with the priority of the cell selected from among the cells that have arrived from preceding input lines as the cell having the highest priority, and again selects the cell with the higher priority.

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Tokyo, Japan

Tomoaki Kawamura