Panasonic Corporation

Socionext Inc.

Tomoaki Ikegami

Kazuyuki Nakanishi

Masaki Tamaru

Hidetoshi Nishimura

First, second, and third power wirings and plurality of first signal wirings are formed on the upper layer of a semiconductor substrate, and at least one second signal wiring is formed on the upper layer of the plurality of first signal wirings. First and second power wirings are mutually separated in the cell height direction and extended in the cell width direction. Third power wiring extends between the first and second power wirings in the cell width direction. The plurality of first signal wirings are separated from first, second, and third power wirings, and electrically connected to at least one of the plurality of circuit elements. At least one second signal wiring extends in the cell width direction, and electrically connected to at least one of the plurality of circuit elements and the plurality of first signal wirings.

Semiconductor integrated circuit device

A standard cell has gate patterns extending in Y direction and arranged at an equal pitch in X direction. End portions of the gate patterns are located at the same position in Y direction, and have an equal width in X direction. A diode cell is located next to the standard cell in Y direction, and includes a plurality of opposite end portions formed of gate patterns that are opposed to the end portions, in addition to a diffusion layer which functions as a diode.

Semiconductor device

A layout structure of a semiconductor integrated circuit is provided with which narrowing and breaking of metal interconnects near a cell boundary can be prevented without increasing the data amount and processing time for OPC. A cell A and a cell B are adjacent to each other along a cell boundary. The interconnect regions of metal interconnects from which to the cell boundary no other interconnect region exists are placed to be substantially axisymmetric with respect to the cell boundary, while sides of diffusion regions facing the cell boundary are asymmetric with respect to the cell boundary.

Semiconductor integrated circuit device having improved interconnect accuracy near cell boundaries

Semiconductor integrated circuit device having metal interconnect regions placed symmetrically with respect to a cell boundary

A semiconductor integrated circuit is provided which entails no increase in the correction time of OPC and in which non-uniformity in the gate lengths due to the optical proximity effects is surely suppressed. A plurality of standard cells (C, C, C, . . . ), each including gates G extended in the vertical direction, are aligned in the transverse direction to form a standard cell row. A plurality of the standard cell rows are located side by side in the vertical direction to form a standard cell group. Each of the standard cell rows has a terminal standard cell Ce at least one end of the standard cell row. The terminal standard cell Ce includes two or more supplementary gates, each of which is any of a dummy gate and a gate of an inactive transistor.

Growing community of inventors

Kanagawa, Japan

Tomoaki Ikegami