Hitachi, Ltd.

Tomoaki Hirai

Seiichi Mita

Terumi Takashi

Naoki Satoh

Yoshiju Watanabe

Shoichi Miyazawa

Yasuhide Ouchi

Akihiko Hirano

Ryushi Shimokawa

Yosuke Hori

Masaki Yoshinaga

Noriaki Hatanaka

Toshihiro Nitta

Yuji Nagaya

Hideki Miyasaka

Koji Shida

Tsuyoshi Hirose

Satoshi Minoshima

Tadao Kaji

Tatsuo Mochizuki

A signal processing circuit for a magnetic recording/reproducing apparatus, including at least an AGC, a PLL, a LPF, an equalizer circuit and a detection circuit, wherein a coefficient compensation circuit is formed by defining a constitution of the equalizer circuit, an error detection circuit is provided which operates by receiving input from the detection circuit, and the LSI is formed by a plurality of analog and digital chips, and the analog and digital chips are connected by current-output type D/A converters connected to at least the AGC and the PLL.

Signal processing circuit and information recording/reproducing apparatus using the same, and method for optimizing coefficients of equalizer circuit

Signal processing circuit and information recording/reproducing

A timing adjusting circuit is provided to define the operating order of a differential amplifier circuit for amplifying read-out signals and an output circuit in order to minimize changes in output DC level. A damping resistor is disposed between two magnetic head terminals and a clamp circuit in a magnetic head driving circuit. To attend to a composite head configuration, short-circuiting with a power supply and a current flowing into the magnetic head during a non-write operation are detected as abnormalities. In addition, short-circuiting and open-circuiting of the magnetic head are also detected as abnormalities. Also, a read circuit is added to a write magnetic head, in order to output read-out signals in a read mode, so that the read-out signals are utilized for detecting errors in read-out signals from an exclusively designed read head or for detecting and correcting such errors.

Read and/or write integrated circuit having an operation timing

A magnetic head circuit for a plurality of magnetic heads includes two emitter follower transistors for receiving magnetic head writing data, two differential transistors connected to the two emitter follower transistors for performing differential operation control thereover, and two resistors connected to collectors of the two differential transistors for supplying a base current to the two emitter follower transistors, and wherein the emitter follower transistors are connected in series with each other to perform differential switch operations over a magnetic head writing current. A magnetic head fly-back voltage has a clamp voltage which varies according to a writing current flowing through a pair of signal terminals. A pair of differential transistors, whose bases are connected to the pair of signal terminals and whose emitters are connected directly to each other, are operated according to a voltage appearing between the pair of signal terminals. Connected to the collectors of the pair of differential transistors are amplification transistors respectively. Connected to outputs of the amplification transistors are post-amplifiers. Such a connection configuration provides a small mirror capacitance as viewed from the bases of the amplification transistors. A high writing and reading accessing speed to the magnetic heads can be realized.

Magnetic head circuit having a write current changeover circuit with a

Growing community of inventors

Odawara, Japan

Tomoaki Hirai