Yamaha Corporation

Tomoaki Ando

Ryo Kamiya

A DSP comprises pipeline registers, a logical operation circuit, a product-sum circuit, DSP registers and an interface. The DSP registers includes at least a plurality of program control registers and excludes the pipeline registers, the logical operation circuit, the product-sum circuit. The interface is connected to the DSP registers, and causes an external device to be capable of writing and reading out from the DSP registers.

Digital signal processor including an interface therein capable of allowing direct access to registers from an external device

A series of digital data to be filtered is divided into a plurality of frames, and f samples of the digital data of each of the frames are burst-transmitted via a computer bus. In transferring the digital data of any one of the frames, n samples of the digital data belonging to a next frame is transferred, along with the digital data of the one frame, to thereby transfer a time series of the digital data consisting of (f&plus;n) samples that are more than the f samples contained in the one frame. Also, a set of k filter coefficients to be used for filtering arithmetic operations in the frame is burst-transmitted via the computer bus, where n&gE;k. Filtering arithmetic processor, such as a DSP, connected to the bus carries out filtering arithmetic processing using the transmitted f&plus;n samples of the digital data and k coefficients, to provide filtered data corresponding to at least the number of samples for a single frame. The filtering arithmetic processing may itself be conducted at high speed asynchronously with a predetermined sampling cycle. Thus, the filtering arithmetic operations are performed intermittently on a frame-by-frame basis. By buffering the filtered data and outputting them with the predetermined sampling cycle, there are provided filtered outputs synchronous with the predetermined sampling cycle. Cross-fade synthesis (interpolation) between filtered data of adjoining frames can smoothly interconnect the filtered data of the frames.

Digital filtering method and device and sound image localizing device

A data write circuit is interposed between a CPU and memory, both of which operate based on the same number of bits (e.g., thirty-two bits). The CPU produces address data for designating a specific address in the memory, and access mode designation data for designating one of a byte access mode, half-word access mode, and word access mode. The data write circuit comprises a decoder for decoding the access mode designation data, a logic circuit for generating selection signals, and four selectors, each of which deals with 8-bit data consisting of eight prescribed bits of the original thirty-two bits. Each selector selects either first data read from the memory or second data output from the CPU. Therefore, each selector is capable of selecting the second data, which are substituted for the first data in the memory. Thus, it is possible to perform write operations in desired units in the memory.

Data write circuit

A control apparatus controls writing and reading of data with respect to a memory which is randomly accessible. An address producing device produces an address by a method according to a predetermined rule, in response to a request to access the memory by the method according to the predetermined rule. A switching device selects one of an address with which the memory is randomly accessed and the address produced by the address producing device. Data is written into and read from the memory, at a location that corresponds to the address that is selected by the switching device and supplied to the memory. It is advantageous to provide a control device which supplies a switching signal to the switching device to cause the switching device to select one of the address with which the memory is randomly accessed and the address produced by the address producing device, depending upon the presence of a request to access the memory by the method according to the predetermined rule and the presence of a request to randomly access the memory.

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Hamamatsu, Japan

Tomoaki Ando