Advanced Micro Devices Corporation

Tommy C Hsiao

Mark T Ramsbey

Yu Nan Sun

Angela Tai Hui

Tuan Duc Pham

Marina V Plat

Robert B Ogle

Lewis N Shen

An improved method of making a flash memory cell including a substrate having a floating gate of a first thickness includes depositing an insulator on the substrate and over the floating gate. The insulator is preferably a high quality oxide. A portion of the insulator not covering the floating gate has a second thickness which is greater than the first thickness of the floating gate. The method further includes polishing the insulator until the second thickness is substantially equal to the first thickness. Polishing results in a planar floating gate and insulator layer. The method further includes sequentially depositing a dielectric layer and a control gate layer on the planar floating gate and insulator layer and then etching these layers to complete the stacked gate structure of the memory cell.

Method of making a memory cell with polished insulator layer

A method and system for providing a semiconductor memory device is disclosed. The method and system include providing a plurality of gate stacks above a substrate. Each of the plurality of gate stacks includes a first edge and a second edge. The method and system also include providing a source implant adjacent to the first edge of each of the plurality of gate stacks and driving the source implant under the first edge of each of the plurality of gate stacks. The method and system also include providing a first spacer and a second spacer for each of the plurality of gate stacks. The first and second spacers are disposed along the first and second edges, respectively, of each of the plurality of gate stacks. The method and system also include providing a drain implant after source implant is driven under the first edge and after the first and second spacers are provided. The drain implant is in the substrate adjacent to the second spacer.

Method and system for reducing short channel effects in a memory device

Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.

Method of manufacturing a semiconductor device without arc loss in peripheral circuit region

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Mountain View, CA, United States of America

Tommy C Hsiao