Ltx Corporation

Formfactor, Inc.

Other

Tommie Edward Berry

Phillip D Burlison

Mark E Deome

Christopher Joel Hannaford

David W Curry

Eric H Rosenfeld

David Menis

Kenneth J Lanier

Roger W Blethen

H Neil Kelly

Jeffrey H Perkins

Edward J Terrenzi

Michael Carlyle Davis

Donald Vick Organ

Alistair Nicholas Sporck

Alexander H Slocum, Jr

Eric D Hobbs

Keith J Breinlinger

Michael Gordon Davis

Marc Loranger

Adrian S Wilson

Methods and apparatus for testing devices using serially controlled intelligent switches have been described. In some embodiments, a probe card assembly can be provided that includes a plurality of integrated circuits (ICs) serially coupled to form a chain, the chain coupled to at least one serial control line, the plurality of ICs including switches coupled to test probes, each of the switches being programmable responsive to a control signal on the at least one serial control line.

Method and apparatus for testing devices using serially controlled intelligent switches

Devices under test (DUTs) can be tested in a test system that includes an aligner and test cells. A DUT can be moved into and clamped in an aligned position on a carrier in the aligner. In the align position, electrically conductive terminals of the DUT can be in a predetermined position with respect to carrier alignment features of the carrier. The DUT/carrier combination can then be moved from the aligner into one of the test cells, where alignment features of the carrier are mechanically coupled with alignment features of a contactor in the test cell. The mechanical coupling automatically aligns terminals of the DUT with probes of the contactor. The probes thus contact and make electrical connections with the terminals of the DUT. The DUT is then tested. The aligner and each of the test cells can be separate and independent devices so that a DUT can be aligned in the aligner while other DUTs, having previously been aligned to a carrier in the aligner, are tested in a test cell.

Test systems and methods for testing electronic devices

Methods and apparatus for testing devices using serially controlled resources have been described. Examples of the invention can relate to an apparatus for testing a device under test (DUT). In some examples, an apparatus can include an integrated circuit (IC) having a serialized input coupled to test circuits, the test circuits selectively communicating test signals with the DUT responsive to a test control signal on the serialized input.

Method and apparatus for testing devices using serially controlled resources

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patterns to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

Single platform electronic tester

An electronic tester with digital, and analog, and memory test circuitry on a single platform. A test head is coupled to a device under test. The device under test can be a system-on-a-chip integrated circuit, a mixed signal integrated circuit, a digital integrated circuit, or an analog integrated circuit. Digital test circuitry applies digital test signals to the device under test coupled to the test head and receives digital outputs from the device under test in response to the digital test signals. Analog test circuitry applies analog test signals to the device under test coupled to the test head and receives analog outputs from the device under test in response to the analog test signals. Memory test circuitry applies memory test patters to the device under test coupled to the test head and receives memory outputs from the device under test in response to the memory test patterns. A tester computer supervises the application of digital, analog, and memory test signals from the digital, analog, and memory test circuitry to the device under test such that signals applied to the device under test can be solely digital test signals, solely analog test signals, solely memory test signals, or mixed digital, analog, and memory test signals. The test head, the digital test circuitry, the analog test circuitry, the memory test circuitry, and the computer are operable as a single platform.

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Pleasanton, CA, United States of America

Tommie Edward Berry