Sanyo Electric Co., Ltd.

Panasonic Intellectual Property Management Co., Ltd.

Tomio Yamashita

Yoshio Okayama

Yusuke Mori

Kazuhiro Sasada

Mamoru Imade

Kazunori Fujita

Haruki Yoneda

Ryo Kuwabara

Mitsuaki Morigami

A method and apparatus for producing a Group III nitride in which the thermal decomposition of the nitrogen element-containing gas is suppressed to enhance the productivity. The method for producing a Group III nitride crystal, comprising: reacting an oxide or a metal of a Group III element under a heated atmosphere to form a compound gas of the Group III element; mixing a nitrogen element-containing gas at a temperature that is lower than that of the compound gas, with the compound gas; and reacting the nitrogen element-containing gas with the compound gas to form a Group III nitride crystal.

Method for producing group III nitride crystal

A semiconductor device includes: an epitaxial layer; a body layer, formed in the epitaxial layer, which includes a channel region; a source layer disposed in superposition on the body layer; a gate insulator, formed on the epitaxial layer, which is in a ring shape surrounding the source layer; a gate electrode formed through the gate insulator; a drift layer, formed in the epitaxial layer, which is in a ring shape surrounding the body layer; and a drain layer formed in the surface of the epitaxial layer and disposed opposite to the source layer. The body layer is disposed such that the boundary surface at an end in the gate-width direction is in contact with the undersurface of the gate insulator. The gate insulator has a thick film portion thicker than a part above the channel region in the gate-length direction at least in a part where the gate insulator is in contact with the boundary surface of the body layer at the end in the gate-width direction.

Semiconductor device

A wiring structure includes a first wiring, a first interlayer dielectric film having a first opening, a second wiring formed with a first recess portion on a region corresponding to the first opening, a second interlayer dielectric film having a second opening and a third wiring so formed as to cover the second interlayer dielectric film, wherein an inner side surface of the second opening is arranged on a region corresponding to the first recess portion and formed such that an opening width of a portion in the vicinity of an upper end increases from a lower portion toward an upper portion.

Wiring structure and method of manufacturing the same

A method for manufacturing a semiconductor device having flat pads. An opening and island-like dielectric films are first formed in a dielectric film. The opening is then filled with metal, and a metal layer is formed on the dielectric film. The upper surface of the metal layer is flattened using the CMP technique with the upper surface of the dielectric film functioning as a stopper. The island-like dielectric films prevent the occurrence of dishing in a conductive portion.

Semiconductor device including an island-like dielectric member embedded in a conductive pattern

A semiconductor device manufacturing method that enables accurate recognition of an alignment mark and optimal formation of a buried wiring. The method includes depositing an insulation film above a semiconductor device, and then etching the insulation film to form a buried wiring hole and an alignment mark pit in the insulation film. Subsequently, a conductive film is deposited on the surface of the insulation film that includes the buried wiring hole and the alignment mark pit. The conductive film is deposited so that it is less than the depth of the alignment mark pit and less than half of a minimum opening width of the alignment mark pit.

Growing community of inventors

Ogaki, Japan

Tomio Yamashita