Renesas Technology Corp.

Hitachi, Ltd.

Renesas Electronics Corporation

Other

Renesas Esatern Japan Semiconductor, Inc.

Tomio Yamada

Shinji Moriyama

Hirokazu Nakajima

Tsuneo Endoh

Mikio Negishi

Nobuyoshi Maejima

Tsutomu Ida

Tomomichi Koizumi

Masashi Yamaura

Hitoshi Watanabe

Kunihiko Nishi

Junichi Saeki

Ichio Shimizu

Takumi Ueno

Toshiyuki Kobayashi

Akira Muto

Toshio Miyamoto

Tomoaki Kudaishi

Hiroshi Kondoh

Eiichi Hase

Masayoshi Yoshimura

Yasutoshi Kurihara

Keizo Otsuki

Yoshihiko Kobayashi

Satoru Konishi

Kazuo Yamazaki

Susumu Sato

Akio Hoshi

Yoshinori Shiokawa

Mamoru Ito

Hiroi Oka

Tooru Fujioka

Michihiko Matsuda

Senji Shoji

Yuji Arai

Atsusi Nakamura

Kouzi Koizumi

Isao Arai

Kazumichi Sakamoto

Saburo Kano

Osami Nomura

Mitsuo Asada

Meiki Ando

Takuzo Taniguchi

Koki Tanimoto

Toshiharu Niitsu

Hiroki Noto

Kazuaki Uehara

Koji Odaira

A hybrid integrated circuit device having high mount reliability includes a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include ones which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Hybrid integrated circuit device and electronic device

A hybrid integrated circuit device having high mount reliability comprises a module substrate which is a ceramic wiring substrate, a plurality of electronic component parts laid out on the main surface of the module substrate, a plurality of electrode terminals laid out on the rear surface of the module substrate, and a cap which is fixed to the module substrate to cover the main surface of the module substrate. The electrode terminals include a plurality of electrode terminals which are aligned along the edges of the module substrate and power voltage supply terminals which are located inner than these electrode terminals. The electrode terminals aligned along the substrate edges are coated, at least in their portions close to the substrate edge, with a protection film having a thickness of several tens micrometers or less. Connection reinforcing terminals consist of a plurality of divided terminals which are independent of each other, and are ground terminals.

Hybrid integrated circuit device, and method for fabricating the same, and electronic device

A semiconductor device comprising semiconductor chips each formed with plural pads at the main surface, chip parts each formed with connection terminals at both ends thereof, a module substrate on which the semiconductor chips and the chip parts are mounted, solder connection portions for connecting the chip parts and the substrate terminals of the module substrate by soldering, gold wires for connecting the pads of the semiconductor chips and corresponding substrate terminals of the module substrate, and a sealing portion formed with a low elasticity resin such as an insulative silicone resin or a low elasticity epoxy resin for covering the semiconductor chips, chip parts, solder connection portions and gold wires which prevents flow out of the solder in the solder connection portion by re-melting thereby preventing short-circuit.

Semiconductor device and a method of manufacturing the same

In a dividing method according to the present invention, a wiring board formed of ceramic is forced up (upper swing) by a lower clamp claw of a clamper, and some of a protruded wiring board portion protruding from a conveying chute is pressed against a support body to perform a first division under bending stress. Thereafter, the upward-located clamper is rotatably swung (lower swing) downward to allow an upper clamp claw to press down the protruded wiring board portion, thereby performing a reverse division at the first division section again as a second division. Since the second division allows a tensile force to act on a remaining and thin non-divided resin portion, the non-divided resin portion is torn off. Thus, the perfect division is enabled. Fractionalizing is done by a one-row division and an individual division so that each semiconductor device is formed.

Manufacturing method of semiconductor device and semiconductor device

A semiconductor device capable of attaining the reduction of size is disclosed. The semiconductor device comprises a module substrate having a surface and a back surface, a control chip mounted on the surface of the module substrate, plural chip parts mounted on the surface in adjacency to the control chip, first and second output chips mounted on the back surface of the module substrate, plural lands formed on the back surface of the module substrate, and a seal portion formed of resin to seal the control chip and the plural chip parts, wherein the first and second output chips are larger in the amount of heat generated than the control chip, the heat from the first and second output ships is radiated to a mother board, and packaging parts on the surface side of the module substrate are sealed with only a sealing resin without using a metallic case or the like to attain the reduction in size of the module.

Semiconductor device and manufacturing the same

There is provided a semiconductor device with enhanced reliability having a heat sink mounting a plurality of semiconductor chips, a plurality of inner leads connected electrically to the semiconductor chips, a molding body for resin molding the plurality of semiconductor chips and the plurality of inner leads, a plurality of wires for providing electrical connections between the respective electrodes of the semiconductor chips and the inner leads corresponding thereto, and wide outer leads connecting to the inner leads and exposed outside the molding body. A plurality of slits are formed in the respective portions of the outer leads located outside the molding body to extend lengthwise in directions in which the outer leads are extracted. This achieves a reduction in lead stress which is placed on the outer leads by thermal stress or the like after the mounting of a MOSFET and thereby enhances the reliability of the MOSFET.

Semiconductor device having an elastic resin with a low modulus of elasticity

In a semiconductor device, the likely occurrence of cracking of a ceramic substrate, and the consequential disconnection of internal layer wiring, due to thermal changes suffered when the semiconductor device is mounted on external wiring boards having different thermal expansion is prevented. The semiconductor device has a ceramic substrate, a wiring pattern formed on a first principal plane and having mounted semiconductor components, an external electrode portion formed on a second principal plane and connected to an external circuit, internal layer wiring formed inside said ceramic substrate to electrically connect said wiring pattern and said external electrode portion via through-hole wiring, and semiconductor components and a resin layer covering said semiconductor components, wherein the internal layer wiring is formed internally with respect to the side of said ceramic substrate with a clearance of at least 0.05 mm.

Semiconductor devices

A semiconductor integrated circuit device is provided for high-frequency or high-speed circuitry having stabilized characteristics and reduced influence on surrounding devices. In the device structure, ground leads extending from a metal substrate or metal layer for mounting ICs for high-frequency or high-speed circuitry are disposed adjacent to at least one side of signal leads and a width W or a space S of at least a part of the leads are set to inherent values for reducing the inductance of ground leads. Further, passive circuit chips for short-circuiting or blocking a high frequency signal are mounted on the metal substrate to suppress high-frequency component signals flowing through power supply leads and ground leads. According to the structure, a high-frequency potential difference due to the inductance of the ground and power supply leads is suppressed and RF energy is confined within the semiconductor integrated circuit device, so that deterioration of the characteristics of the high-frequency or high-speed ICs can be reduced and leakage of the RF signal to the outside of the semiconductor integrated circuit device can be prevented to avoid influence on surrounding devices.

Semiconductor integrated circuit devices for high-speed or high frequency

In a semiconductor device having a number of pins, there is used an inner lead group comprising a group of upper inner leads 7A present in an upper plane and a group of lower inner leads 7B in a lower plane, the upper inner lead group and the lower inner lead group being laminated together in an insulated from each other through an insulating layer 2C, both end portions in the circumferential direction of each upper inner lead 7A being overlapped with circumferential ends of adjacent lower inner leads 7B, 7B located on both sides of the upper inner lead, and bonding areas 8A of the upper inner leads 7A being positioned radially outwards with respect to bonding areas 8B of the lower inner leads 7B, whereby the pitch between inner leads can be reduced to half, and the number of pins can be increased under the condition that the size of a resin sealing body 24 is fixed. Further, wire bonding can be done properly because a reaction force induced at the time of wire bonding for the upper inner leads 7A is borne at the overlapped portions of the lower inner leads 7B, 7B.

Semiconductor device and method of fabricating same, as well as lead

Growing community of inventors

Komoro, Japan

Tomio Yamada