Nec Corporation

Tomio Takiguchi

Takeshi Ogawara

A bipolar transistor is provided with a collector layer of a first conductive type, a base layer of a second conductive type formed at a surface of the collector layer, and an emitter layer of the first conductive type formed at a surface of the base layer. An emitter electrode is connected to the emitter layer. Base electrodes are connected to the base layer and surround the emitter electrode. Emitter electrodes are connected to the collector layer and surround the base electrodes.

Bipolar transistor and semiconductor device having the same

A reference voltage supply circuit is provided with a PNP transistor. The PNP transistor has an N-type well for a base formed at a surface of a P-type semiconductor substrate. The reference voltage supply circuit is further provided with a resistor element connected to an emitter of the PNP transistor. The resistor element has an N-type well for a resistor at the surface of the P-type semiconductor substrate. The well is fabricated at the same time as when the N-type well for a base is fabricated.

Reference voltage supply circuit having reduced dispersion of an output voltage

Reference voltage supply circuit

The different signal generation circuit has a first transistor MP2 connected between a first power supply line Vcc and a first output terminal OTP and a gate connected to a first node, a second transistor MN2 connected between the first output terminal OTP and a second power supply line GND and a gate connected to a second node, and a delay circuit 31 and 13 connected between the first node and the second node.

Differential signal generating circuit having current spike suppressing

The D/A converting device disclosed includes a decoder, and a plurality of unit current generating circuits each having a differential switching circuit and a reference voltage generating circuit. The decoder receives a digital input value of n bits and outputs a plurality of complementary pairs of digital signals corresponding to the n bits of the digital input value. Each unit current generating circuit receives a complementary pair of digital signals from the decoder. The differential switching circuit has two complementary current output terminals, a bias voltage input and a reference voltage input. The two complementary current output terminals of the differential switching circuit are interconnected between corresponding ones of the unit current generating circuits with the interconnected points being made two complementary analog output terminals. Each of the analog output terminals and a power source terminal are connected to a load circuit, whereby analog output voltages corresponding to the digital signals inputted to digital input terminals of the n bits are obtained at the analog output terminals. This enables the speeding up of a settling time by reducing overshoot and undershoot when the analog output full-swings.

Digital/analog (D/A) converting device with unit current generating

A constant current source is connected to a first node that connects on the one hand to a predetermined potential via a first switching transistor with a control electrode thereof connected to a signal input terminal, a second node, and a resistive conduction member, and on the other hand to a current output terminal via a second switching transistor with a control electrode thereof connected to the second node to constitute a current switching circuit operable without an external reference bias and with a reduced number of components.

Current switching circuit operable at high speed without externally

A digital-to-analog converter having a main analog conversion part which carries out digital to analog conversion of input digital signals, an auxiliary analog conversion part which compensates the digital-to-analog conversion error, a memory circuit which accumulates the compensation data for compensating the conversion error, a register circuit which inputs the output signal of the memory circuit, and a matrix switching circuit which selects the output signal of the register circuit by means of the higher order bits of the input digital signal. Prior to the start of the digital-to-analog conversion operation the compensation data accumulated in the memory circuit are transferred to the register circuit. Later, at the time of the digital to analog conversion operation the matrix switching circuit is controlled by means of the higher order bits of the input digital signal selects the data held in the register circuit, and carries out the compensation of the error in the analog conversion.

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Tokyo, Japan

Tomio Takiguchi