Fujitsu Corporation

Fujitsu Vlsi Limited

Tomio Nakano

Yoshihiro Takemae

Masao Nakano

Kimiaki Sato

Junji Ogawa

Norihisa Tsuge

Tsuyoshi Ohira

Takashi Horii

Shigeki Nozaki

Takeo Tatematsu

Hirohiko Mochizuki

Yasuhiro Fujii

Katsuhiko Kabashima

Fumio Baba

Hidenori Nomura

Norihisa Tsuge, Deceased

Yoshiharu Kato

Teruo Seki

Kiyoshi Miyasaka

Akihiro Iwase

Nobumi Kodama

Sachie Tsuge

Itaru Tsuge

Masaru Satoh

A semiconductor device with an expanded range of a recommended condition for an input voltage is disclosed. In embodiment, the semiconductor device having input protection on an input terminal thereto, includes: a semiconductor region having a first conducting type, first and second diffusion regions defined in the semiconductor region and respectively having a second conducting type, and a transistor formed by using the semiconductor region as a base, the first diffusion region as a collector, and the second diffusion region as an emitter. The first diffusion region is connected to one of a high-potential power supply and a low-potential power supply, the second diffusion region is connected to the input terminal, and the semiconductor region is connected to another power supply having a voltage high enough to reverse bias the junction between the semiconductor region and the first diffusion region.

Semiconductor device having input protective function

In a semiconductor integrated circuit for taking in an external power source voltage from outside the semiconductor chip, the external power source voltage is dropped by a voltage dropping unit installed inside the semiconductor chip and the external power source voltage in the semiconductor integrated circuit, as dropped is supplied as an internal power source voltage to the semiconductor chip and used as the internal power source voltage, a plurality of voltage dropping units are installed for each of a plurality of semiconductor circuit block installed inside the semiconductor chip, and the voltage fluctuation of an internal power source is effectively suppressed in the event that a circuit consuming a very high current is operated.

Voltage reducing circuit

A complementary semiconductor memory device comprises a memory cell array (73, 100) in which each cell (MC.sub.p ; MC.sub.po) has a first MIS transistor (Q.sub.p); Q.sub.p1, Q.sub.p2) of a first conduction type connected to a word line, a decoding circuit (71) for decoding an input address signal and generating a selecting signal, and a driving circuit (72; 90) having a second MIS transistor (W.sub.80) of a second conduction type opposite to the first conduction type for driving the word line, thereby improving the operation speed thereof, while decreasing the possibility of the destruction of information in each cell by .alpha.-rays. A word drive signal having a negative potential may be used, and the threshold voltage of the second MIS transistor is selected to be greater than an absolute valve of the threshold voltage of the first MIS transistor.

Complementary semiconductor memory device including cell access

A dynamic random access memory including: a memory constituted by a plurality of dynamic type memory cells; a refresh control circuit for refreshing the memory cells by controlling a refresh address circuit in a refresh mode; an address latch circuit for latching an external address signal in a read/write mode and latching a refresh address signal in the refresh mode; a clock generating circuit for generating a second clock and a third clock based on a first clock obtained after a predetermined delay time from a trailing edge of a row address strobe signal, the second clock controlling a first timing for taking the external address signal into the address latch circuit in the read/write mode, and the third clock is generated after the second clock and controls a second timing for taking the refresh address signal into the address latch circuit in the refresh mode.

Dynamic random access memory having improved refresh timing

A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.

Semiconductor memory device with internal control signal based upon

A semiconductor memory device having a memory cell array constituted by a plurality of memory cell blocks includes a clock generator unit constituted by a plurality of clock generator sections, each of the clock generator sections corresponding to each of the memory cell blocks, and a block selector unit for selecting one of the clock generator sections in correspondence with the row address of a designated address. Accordingly, only a clock generator section corresponding to the selected memory cell block is operated by the designated address.

Semiconductor memory device capable of selective operation of memory

A semiconductor integrated circuit device having a fuse-blown type ROM for storing information concerning defective bits for the replacement of defective bits in a semiconductor memory device, etc., with redundant bits. The integrated circuit device comprises fuses for constituting the ROM, pads for supplying a melting current to the fuses, and PN junctions each being formed, for example, by a semiconductor substrate and a diffusion layer formed on the semiconductor substrate. Each of the fuses is melted by applying voltage to a circuit connecting the PN junction, the fuse, and the pad so that the PN junction is forward biased, thereby supplying a large current to the fuse.

Integrated circuit device

A semiconductor device has a substrate of a first conductivity type including a well of a second conductivity type opposite to the first conductivity type. The semiconductor device comprises a bias potential generating circuit for generating a potential in the substrate or the well; a potential detecting circuit for detecting a potential of the substrate or the well and a gate circuit. The gate circuit is connected to the potential detecting circuit and to an internal circuit and applies an enable signal to the internal circuit in accordance with the detected potential of the substrate or the well. Consequently, latch-up of parasitic transistors in a CMIS-inverter circuit of the semiconductor device can be prevented.

Complementary semiconductor device reducing latch-up phenomenon

A semiconductor memory device including: a substrate; a plurality of word lines; a plurality of bit lines; and a plurality of memory cells, each positioned at an intersection defined by one of the word lines and one of the bit lines and including a transfer transistor and a capacitor. Each of the memory cells has a first insulating layer covering a gate of the transfer transistor. The capacitor in each memory cell includes a second conductive layer which contacts one of source and drain regions of the transfer transistor in the memory cell, through the first insulating layer, and extends over the gate of the transfer transistor, a second insulating layer formed on the first conductive layer, and a second conductive layer extending over the second insulating layer. The semiconductor memory device further includes an additional conductive layer directly connected to the other of the source and drain regions of the transfer transistor in the memory cell, through the first insulating layer covering same, and extending over the gate of the adjoining transfer transistors. Each bit line is connected to the other of the source and drain regions through the additional conductive layer. A method for manufacturing a semiconductor memory device having the above construction.

Semiconductor memory device having stacked-capacitor type memory cells

A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.

Semiconductor integrated circuit with redundant circuit replacement

A dynamic semiconductor memory device including memory cells divided into a plurality of blocks (1-1, 1-2). A simultaneous write enable circuit performs a write operation simultaneously upon the plurality of blocks, and a comparison circuit compares read data of one block with read data of the other block, thereby carrying out a test.

Dynamic semiconductor memory device having a simultaneous test function

A semiconductor memory device capable of compensating for variation in a discriminating voltage of a memory cell comprising a memory cell and a gate circuit for coupling the memory cell to a bit line. The device has a precharge circuit for precharging the bit line pair to a predetermined resultant precharge voltage in a reset state. The precharge circuit precharges a bit line pair with the resultant precharge voltage obtained by adding a compensating voltage to a precharge voltage in the reset state. The compensating voltage is adapted to compensate for variation in a memory cell discriminating voltage based on variation in a memory cell voltage caused by capacitive coupling of a word line to a memory capacitor due to a parasitic capacitance of a gate circuit in the active state, and the precharge voltage is adapted to optimize the memory cell discriminating voltage when it is assumed that the parasitic capacitance is not present.

Semiconductor memory device having a circuit for compensating for

A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse. In a normal operation, the voltage output from the voltage level conversion circuit can be set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse to which the voltage is applied, but higher than the threshold voltage of the information detection circuit.

Semiconductor integrated circuit device having fuse-type information

A semiconductor memory device has an operational mode such as a nibble mode or page mode, a first address strobe signal is kept in an active state, and a second address strobe signal is successively switched between an active state and standby state, thereby enabling successive data output. Previous output data is reset once, in accordance with the switchover of the second address strobe signal to the active state while the first address strobe signal is in the active state, before outputting data, and the reset operation for outputting is also performed when both the first and second address strobe signals are switched to the standby state, so that the period in which the data is output is expanded.

Semiconductor memory device having extended period for outputting data

In a semiconductor memory device including word lines (WL) and bit lines (BL), a regular pattern circuit area comprising elements regularly arranged in line with the word lines and/or the bit lines is divided into a plurality of blocks (1-1, 1-2). Provided between the divided blocks are irregular or peripheral circuit areas (2). Provided outside of the divided blocks are pads (P.sub.1 to P.sub.16).

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Kawasaki, Japan

Tomio Nakano