Kabushiki Kaisha Toshiba

Tomie Yamamoto

Masahiro Abe

Yasukazu Mase

As shown in FIG. , a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

Wiring pattern of semiconductor integrated circuit device

As shown in FIG. 4, a wiring pattern of a semiconductor integrated circuit device of the present invention comprises a wiring portion extending from a connection hole and a connection portion located on the connection hole and having a matching allowance with respect to said connection hole on said wiring portion side being formed wider than a predetermined matching allowance by a predetermined width with which a required yield of successful matching can be assured.

Method for patterning wirings of semiconductor integrated circuit device

A semiconductor device has a first interconnection pattern formed on a semiconductor substrate, and a second interconnection pattern located in and over a through hole formed at a composite insulating layer structure. The composite insulating layer structure is constituted by a first inorganic insulating film and an organic insulating film. At a peripheral region of the second interconnection pattern, the organic insulating film is partially eliminated to form an eliminated portion. The semiconductor device also has a second inorganic insulating film which is formed over the organic insulating film and is directly formed on the first inorganic insulating film, via the eliminated portion.

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Yokohama, Japan

Tomie Yamamoto