Qualcomm Incorporated

Tomer Rafael Ben-Chen

Sharon Graif

Lior Amarilio

Shaul Yohai Yifrach

Amit Gil

Ron Keidar

Igor Malamant

David Teb

Punit Kishore

Yaron Shachar

Meital Zangvil

Dan Gilboa Waizman

Yitzhak Sabo

Deepak Jindal

Ayala Miller

Systems and method for lane management in a communication bus are disclosed. In one aspects, a communication link or bus between a baseband processor (BBP) and a radio frequency integrated circuit (RFIC) may include multiple uplink lanes for transmission and multiple downlink lanes for reception that are frequency constrained and adjust bandwidth by adjusting duty cycles on the lanes. To reduce power consumption by the communication bus, exemplary aspects of the present disclosure contemplate using in-band signaling to turn off lanes selectively during inactive periods such that the lanes do not duty cycle in tandem with active lanes. Additionally, in some aspects, the uplink lanes may be continuously active during transmission while the downlink lanes are turned off. This dynamic lane usage reduces power consumption, does not require additional pins for sideband signaling, and does not introduce any additional latency.

Systems and methods for lane management in a communication bus

High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

High-speed communication link with self-aligned scrambling

The disclosure includes systems and methods for bus control. A method comprises receiving a data exchange request, wherein the data exchange request includes a data exchange tag that identifies a data exchange, splitting the data exchange into a plurality of fractional data transactions, providing one or more bus commands to a system bus, receiving, at the bus controller, one or more acceptance notifications indicating that the one or more of the plurality have been accepted by the system bus, assigning transaction identifiers (TIDs) corresponding to the one or more of the plurality of fractional data transactions, receiving one or more completion notifications indicating that the one or more of the plurality have been completed, determining that each of the plurality of fractional data transactions associated with the data exchange tag have been completed, and notifying the processor that the requested data exchange has been completed.

Bus controller and related methods

Methods and apparatuses for aggregated IBIs are provided. The apparatus includes a host controller configured to communicate with at least one slave via a serial communication bus, trigger and receive a series of responses from the at least one slave via the serial communication bus, determine one response of the series of responses indicating an in-band interrupt (IBI) request, and respond to the IBI request based on a position of the one response among the series of responses. The method includes communicating with at least one slave via a serial communication bus, triggering and receiving a series of responses from the at least one slave via the serial communication bus, determining one response of the series of responses indicating an in-band interrupt (IBI) request, and responding to the IBI request based on a position of the one response among the series of responses.

Aggregated in-band interrupt based on responses from slave devices on a serial data bus line

A method of in-system structural testing of a system-on-chip (SoC) using a peripheral interface port is described. The method including enabling a scan interface controller of the SoC through the peripheral interface port. The method also includes streaming structural test patterns in the SoC through the scan interface controller.

In-system structural testing of a system-on-chip (SoC) using a peripheral interface port

Systems, methods, and apparatus are described for communicating virtual GPIO (VGI) information between multiple source devices and multiple consuming devices. A method for facilitating communication of VGI state over a serial bus includes determining that an in-band interrupt has been asserted on the serial bus while the serial bus is idle, participating in an exchange of VGI state when a first bit of a device address transmitted during bus arbitration associated with the in-band interrupt has a first value, receiving a plurality of bits of VGI state during the exchange of VGI state, including bits transmitted by multiple devices coupled to the serial bus, and mapping at least one bit in the plurality of bits of VGI state to a physical GPIO pin. Transmission of at least a second bit of the device address is suppressed when the first bit of a device address has the first value.

Low latency virtual general purpose input/output over I3C

Hardware-based packet processing circuitry is provided. In this regard, hardware-based packet processing circuitry includes header processing circuitry and payload processing circuitry. The hardware-based packet processing circuitry receives a header portion and a payload portion of an incoming packet in a first packet format. The header processing circuitry and the payload processing circuitry process the header portion and the payload portion to form a processed header portion and a processed payload portion, respectively. The hardware-based packet processing circuitry generates an outgoing packet in a second packet format based on the processed header portion and the processed payload portion. By processing the incoming packet separately in the header processing circuitry and the payload processing circuitry, it is possible to accelerate selected steps (e.g., ciphering/deciphering, compression/de-compression, checksum, etc.) of packet processing via dedicated hardware functional block(s), thus reducing computing resource requirement and overhead associated with software-based packet processing.

Hardware-based packet processing circuitry

This disclosure describes devices, systems and techniques relating to a dongle device that is designed to provide broadcast video capabilities to an electronic device. In one example, a dongle device is configured to communicatively couple to an electronic device, wherein the dongle device comprises a multimedia receiver that receives a broadcast that includes multimedia data, and a web server that communicates the multimedia data to a web browser of the electronic device.

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Amikam, Israel

Tomer Rafael Ben-Chen