Intel Corporation

Tomer Fael

Adee Ofir Ran

Itamar Fredi Levin

Ariel Cohen

Mingming Xu

Yoel Krupnik

Dror Lazar

Kevan A Lillie

Ram Livne

Ro'ee Eitan

Vladislav Tsirkin

Alexander Pogrebinsky

Dima Hammed

Elior Segev

One embodiment provides an enhanced slicer. The enhanced slicer includes a first clocked comparator circuitry and a current path circuitry. The first clocked comparator circuitry includes a first comparator circuitry, a first latch circuitry, a first output node (Out_P) and a second output node (Out_N). The current path circuitry is coupled to the output nodes and a reference node. The current path circuitry is to enhance current flow between at least one of the output nodes and the reference node, in response to a clock signal.

Slicer and decision feedback equalization circuitry

Various embodiments are generally directed to techniques for testing a receiver incorporated into an IC to receive a bitstream. An apparatus includes a precharge component to set a VGA to output a differential bias voltage; a taps component to set a tap to form a feedback loop that extends from an output of the bit slicer to the input of the bit slicer through a delay circuit and the tap, the tap to output a first differential voltage to the input of the bit slicer to invert a polarity of a sum of differential voltages at the input of the bit slicer to enable oscillation of the bit slicer, the sum generated from at least the differential bias voltage and the first differential voltage; and a capture component coupled to the output of the bit slicer to capture a series of bit values therefrom. Other embodiments are described and claimed.

Techniques for testing receiver operation

Growing community of inventors

Jerusalem, Israel

Tomer Fael