Intel Corporation

Hiel Corporation

Tomer Bar-On

Hugues Labbe

John G Gierach

Jacob Subag

Jeremie Dreyfuss

Yaniv Fais

Lev Faivishevsky

Amit Bleiweiss

Abhishek R Appu

Travis T Schluessler

Tomer Schwartz

Joydeep Ray

Gabor Liktor

Andrew T Lauritzen

Uzi Sarel

Gal Leibovich

Amitai Armon

Michael Behar

Guy Jacob

Ankur N Shah

Kai Xiao

Ehud Cohen

Yahav Shadmiy

Prasoonkumar Surti

Adam T Lake

Devan Burke

Itamar Ben-Ari

Altug Koker

Abhishek Venkatesh

Balaji Vembu

Nikos Kaburlasos

John H Feit

Jacek Kwiatkowski

Elmoustapha Ould-Ahmed-Vall

Subramaniam M Maiyuran

Vasanth Ranganathan

Guei-Yuan Lueh

Karthik Vaidyanathan

Atsuo Kuwahara

David M Puffer

Carsten Benthin

Jonathan Kennedy

Galina Ryvchin

Eran Ben-Avi

Neta Zmora

Eyal Yaacoby

Michael Apodaca

Deepak Shashidhar Vembar

Sameer Kp

Johannes Guenther

Raanan Yonatan Yehezkel Rohekar

Gal Novik

Zigi Walter

Orly Weisel

Shira Hirsch

Yarden Oren

Eriko Nurvitadhi

Peter L Doyle

Philip R Laws

Oguz Hasan Elibol

Dhawal Srivastava

Anil Thomas

Gokce Keskin

Sameer K P

Pruthvi Gowda Thorehosur Appajigowda

Nishant Patel

Huma Abidi

Jaikrishnan Menon

Amital Armon

David Puffer

In an example, an apparatus comprises a plurality of execution units, and a first memory communicatively couple to the plurality of execution units, wherein the first shared memory is shared by the plurality of execution units and a copy engine to copy context state data from at least a first of the plurality of execution units to the first shared memory. Other embodiments are also disclosed and claimed.

Engine to enable high speed context switching via on-die storage

Systems, apparatuses and methods may provide for technology that receives, at a topology shader in a graphics pipeline, an object description and generates, at the topology shader, a set of polygons based on the object description. Additionally, the set of polygons may be sent to a vertex shader.

Topology shader technology

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.

Motion biased foveated renderer

In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to receive a plurality of data inputs for training a neural network, wherein the data inputs comprise training data and weights inputs; represent the data inputs in a first form; and represent the weight inputs in a second form. Other embodiments are also disclosed and claimed.

Real time context dependent deep learning

In an example, an apparatus comprises logic, at least partially including hardware logic, to implement a lossy compression algorithm which utilizes a data transform and quantization process to compress data in a convolutional neural network (CNN) layer. Other embodiments are also disclosed and claimed.

Low rank matrix compression

An embodiment of a graphics apparatus may include a mask buffer to store a mask, a shader communicatively coupled to the mask buffer to apply the mask to a first shader pass, and a resolver communicatively coupled to the mask buffer to apply the mask to a resolve pass. The resolver may be configured to exclude a sample location not covered by the mask in the resolve pass. Other embodiments are disclosed and claimed.

Graphics anti-aliasing resolve with stencil mask

An apparatus to facilitate compute optimization is disclosed. The apparatus includes a at least one processor to perform operations to implement a neural network and compute logic to accelerate neural network computations.

Compute optimization mechanism for deep neural networks

In an example, an apparatus comprises a plurality of execution units comprising and logic, at least partially including hardware logic, to traverse a solution space, score a plurality of solutions to a scheduling deep learning network execution, and select a preferred solution from the plurality of solutions to implement the deep learning network. Other embodiments are also disclosed and claimed.

Scheduling configuration for deep learning networks

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to expose embedded cast operations in at least one of a load instruction or a store instruction; determine a target precision level for the cast operations; and load the cast operations at the target precision level. Other embodiments are also disclosed and claimed.

Variable precision and mix type representation of multiple layers in a network

Systems, methods and apparatuses may provide for technology to reduce rendering overhead associated with light field displays. The technology may conduct data formatting, re-projection, foveation, tile binning and/or image warping operations with respect to a plurality of display planes in a light field display.

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

Growing community of inventors

Petah Tikva, Israel

Tomer Bar-On