International Business Machines Corporation

Tomer Abraham Cohen

Noam Jungmann

Elazar Kachir

Hezi Shalom

Israel A Wagner

Yaron Freiman

Doris Bittruf

Muhammad Suleiman

In an approach, a processor identifies a current cell depicted in an integrated circuit layout tool, the current cell of a hierarchical layout comprises a plurality of cells. A processor generates an overlay, the overlay comprising an abstraction of at least one object present in a higher level of the hierarchical layout that overlaps with the current cell. A processor projects the overlay onto the current cell.

Hierarchy-aware integrated circuit layout design

A clock gating method and circuit for avoiding out-of-spec clock operations. The circuit comprises a clock gating section that gates a clock signal according to an enabling signal generated by an enabling signal controller, the enabling signal controller generating the enabling signal according to a set signal and a reset signal. The circuit further comprises a set signal generator that generates the set signal, a reset signal generator that generates the reset signal, and a feedback section that uses the enabling signal to generate the feedback signal for the reset signal generator. The reset signal generator generates the reset signal by using the feedback signal. The enabling signal controller further generates an acknowledgement signal having a high signal during a blocking period when the clock signal is blocked and utilizes the acknowledgement signal as an announcement to a higher circuit that the clock signal is blocked.

Clock gating circuit for avoiding out-of-spec clock operations in self-timed circuits

A system, program product, and method for processing synchronized memory repairs. The method includes identifying a faulty memory row from a plurality of functioning memory rows in a memory array. The method also includes executing memory row repair operations directed toward the faulty memory row and identifying a repair row to operationally replace the faulty memory row. The method also includes creating a multiple hot state within a memory decoder. The memory decoder includes logic circuitry for executing operation of the plurality of functioning memory rows. The method further includes activating a wordline of the identified repair row through the multiple hot state, and executing one or more memory operations on the identified repair row though the memory decoder. Accordingly, the embodiments disclosed herein facilitate synchronization of the repair row and functioning memory rows within the memory array, as well as any associated peripheral signals.

Synchronized memory repair system (SRS)

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Binyamina, Israel

Tomer Abraham Cohen