Infineon Technologies Ag

Panthronics Ag

Tomaz Felicijan

Berndt Gammel

Stefan Mangard

Jakob Jongsma

Michael Pieber

Andrea Hoeller

Jan Crols

Hamzeh Nassar

Walter Mergler

A device () that processes a Near Field Communication type application which device () comprises: a host controller circuit () that processes device applications, that use the Near Field Communication type application, and that processes a host driver () that communicates based on a first interface protocol (NCI; EMV); a NFC controller circuit () that processes a Near Field Communication type contactless interface () and a controller driver () that interfaces with the host controller circuit (), wherein the host controller circuit () processes a first transmission module () that interfaces with the host driver () based on the first interface protocol (NCI; EMV) and with the controller driver () based on a second interface protocol, which first transmission module () furthermore processes substantially all none-time critical and/or memory consuming tasks of the Near Field Communication type application and wherein the NFC controller circuit () comprises a second transmission module () that processes all time critical tasks for the Near Field Communication type application towards the Near Field Communication type contactless interface ().

NFC 'split stack' architecture

An embodiment relates to a device for a memory access, the device having a first component for conducting operations on the memory and a second component for accessing the memory in a randomized manner, wherein the first component conducts at least a portion of the operations via the second component.

Randomized memory access

In various embodiments an arithmetic logical unit array is provided, which may include: at least two data registers for storing data, a plurality of fixed instruction registers for storing machine code instructions, and at least one programmable instruction register for storing instruction data being representative for a machine code instruction. A selection circuit of the arithmetic logical unit array may be configured to select one of the machine code instructions from the fixed instruction registers or the machine code instruction represented by the instruction data. An arithmetic logical unit of the arithmetic logical unit array may be configured to apply an operation in accordance with the machine code instruction selected by the selection circuit to the data stored in the data registers.

Arithmetic logical unit array, microprocessor, and method for driving an arithmetic logical unit array

According to one embodiment, a permutation generator is described comprising a memory configured to store, for each number of a predetermined set of numbers, whether the number has already been included in a number sequence; a receiver configured to receive a random number; a determiner configured to select a number from those numbers of the set of numbers that have not yet been included in the number sequence as next element of the number sequence based on the random number and an output configured to output the selected number as the next element of the number sequence.

Random permutation generator and method for generating a random permutation sequence

According to one embodiment, a processing device for multiplying a first polynomial with a second polynomial is described including a first memory storing a representation of the first polynomial, a controller configured to separate the first polynomial into parts, a second memory storing pre-determined results of the multiplications of the second polynomial with possible forms of the parts of the first polynomial, a third memory for storing the result of the multiplication, an address logic, configured to determine, for each part of the first polynomial, a start address of a memory block of the second memory based on the form of the part and the location of the part within the first polynomial and an adder configured to add, for each determined address of the memory block of the second memory, the content of the memory block of the second memory at least partially to the contents of the third memory, wherein the data element of the third memory to which the content of a data element of the memory block of the second memory is added is the same for a plurality of the parts of the first polynomial.

Processing device and method for multiplying polynomials

A computational system is configured to protect against integrity violation. The computational system includes a processing unit and a critical resource, the critical resource being controllable by the processing unit so as to be locked or unlocked. The critical resource is configured to intermittently transmit a polling value to the processing unit, and the processing unit is configured to apply a transformation onto the polling value so as to obtain a response value and send the response value back to the critical resource. The critical resource is configured to check the response value on correctness so as to obtain a check result, and subject the controllability to a dependency on the check result.

Growing community of inventors

Graz, Austria

Tomaz Felicijan