Intel Corporation

Tomasz Janczak

Altug Koker

Louis Feng

Andrew T Lauritzen

David M Cimini

Abhishek R Appu

Prasoonkumar Surti

Travis T Schluessler

Abhishek Venkatesh

Joydeep Ray

Subramaniam M Maiyuran

Nikos Kaburlasos

Kai Xiao

Devan Burke

Slawomir Grajewski

Ben J Ashbaugh

Elmoustapha Ould-Ahmed-Vall

Balaji Vembu

Sanjeev S Jahagirdar

Kamal Sinha

Guei-Yuan Lueh

Ali-Reza Adl-Tabatabai

Karthik Vaidyanathan

Linda L Hurd

Kiran Chand Veernapu

David M Puffer

Tatiana Shpeisman

Rajkishore Barik

John H Feit

Jacek Kwiatkowski

Wenyin Fu

Josh B Mastronarde

Bhushan M Borole

Philip R Laws

Jayanth N Rao

Eric J Asperheim

Yang Ni

Murali Ramadoss

Michael Apodaca

Robert M Toth

Kalyan Kumar Bhiravabhatla

Izajasz Piotr Wrosz

Carl Jacob Munkberg

Larry D Seiler

Marco Salvi

Franz Petrik Clarberg

Aaron Eliot Lefohn

Marek Targowski

Wieslaw Wisniewski

An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, an object space adjuster communicatively coupled to the graphics subsystem to adjust an object space parameter based on a screen space parameter, and a sample adjuster communicatively coupled to the graphics subsystem to adjust a sample parameter of the graphics subsystem based on a detected condition. Other embodiments are disclosed and claimed.

Graphics with adaptive temporal adjustments

In an example, an apparatus comprises a plurality of execution units comprising at least a first type of execution unit and a second type of execution unit and logic, at least partially including hardware logic, to analyze a workload and assign the workload to one of the first type of execution unit or the second type of execution unit. Other embodiments are also disclosed and claimed.

Hybrid low power homogenous grapics processing units

Systems, apparatuses and methods may provide for technology that detects a memory fence in a thread, adds a group identifier to one or more memory operations in the thread that follow the memory fence, and sends the one or more memory operations and the group identifier to a memory structure. In one example, the group identifier is used to track completion of the one or more memory operations.

Handling surface level coherency without reliance on fencing

An embodiment of a graphics processor pipeline apparatus may include a vertex fetcher to fetch vertices, a vertex shader communicatively coupled to the vertex fetcher to shade the fetched vertices, a primitive assembler communicatively coupled to the vertex shader to assemble primitives, and a primitive replicator communicatively coupled to the primitive assembler to replicate primitives for at least a first and a second viewport.

Replicating primitives across multiple viewports

An embodiment of a graphics pipeline apparatus may include a vertex shader, a visibility shader communicatively coupled to an output of the vertex shader to construct a hierarchical visibility structure, a tile renderer communicatively coupled to an output of the vertex shader and to the visibility shader to perform a tile-based immediate mode render on the output of the vertex shader based on the hierarchical visibility structure, and a rasterizer communicatively coupled to an output of the tile renderer to rasterize the output of the tile renderer based on the hierarchical visibility structure. Other embodiments are disclosed and claimed.

Tile-based immediate mode rendering with early hierarchical-z

Systems, methods and apparatuses may provide for deferred geometry rasterization technology that includes a decision controller to determine, based on available resources in a graphics processor and a view frustum, a first portion of graphics information to be output to the graphics processor and a storage device communicatively coupled to the decision controller to store a second portion of the graphics information for future use. Additionally, an output handler may output the first portion of the graphics information to the graphics processor and swap out the second portion for unused graphics information on the graphics processor.

Deferred geometry rasterization technology

Systems, apparatuses and methods may provide for technology that detects, by a current stage of a hardware pipeline, a flush request with respect to a first resource and executes, by the current stage, one or more transactions associated with a second resource. Additionally, the current stage may conduct one or more flush operations with respect to the first resource, wherein the one or more transactions associated with the second resource are executed after detection of the flush request and before the one or more flush operations.

Resource-specific flushes and invalidations of cache and memory fabric structures

Systems, apparatuses and methods may provide for technology that computes, by a shader in a fixed-functionality hardware shader library, a physically based shading model for a type of material. Additionally, the shader may shade one or more surfaces associated with the type of material in accordance with the physically based shading model. In one example, two or more shaders in the shader library are dedicated to different types of materials.

Physically based shading via fixed-functionality shader libraries

An apparatus and method are described for asynchronous texel shading. For example, one embodiment of a graphics processing apparatus comprises: a first shader to perform shading operations on a plurality of pixels in a first pass and to submit a request to shade texels; and a texel shader to responsively perform texel shading operations in response to the request from the first shader, the texel shader to write results to a procedural texture stored in a memory subsystem, the procedural texture to be read during a second pass by the first shader or another shader.

Apparatus and method for asynchronous texel shading

Systems and methods for avoiding additional processing during generation of a procedural texture are disclosed. In one embodiment, a graphics processor includes memory to store graphics data and control data of a procedural texture. A texel shader dispatch circuitry is coupled to the memory. The texel shader dispatch circuitry is configured to maintain coherency between local memory of the texel shader dispatch circuitry during generation of the procedural texture via communication with the procedural texture to avoid overshading.

Systems and method for avoiding duplicative processing during generation of a procedural texture

An embodiment of a graphics apparatus may include a tile candidate identifier to determine if a compute kernel is a tile candidate, and a compute kernel tiler communicatively coupled to the tile candidate identifier to tile the compute kernel if the compute kernel is determined to be a tile candidate. Other embodiments are disclosed and claimed.

Graphics processor with tiled compute kernels

Growing community of inventors

Gdansk, Poland

Tomasz Janczak