Intel Corporation

Tomasz Bujewski

Subramaniam M Maiyuran

Guei-Yuan Lueh

Jorge E Parra

Supratim Pal

Chandra S Gurram

Konrad Trifunovic

Pratik J Ashar

Wei-Yu Chen

Jorge F Garcia Pabon

Weiyu Chen

Raghavendra Miyar

Radoslaw Drabinski

Rajarshi Bajpayee

An processor to facilitate register sharing is disclosed. The processor includes a plurality of execution units (EUs), each including a General Purpose Register File (GRF) having a plurality of registers; and register sharing hardware to divide the plurality of registers into a first set of registers dedicated for execution of a first set of threads and a second set of registers shared for execution of a second set of threads.

Register sharing mechanism

A processor is disclosed. The processor includes an execution unit having a register file having one or more banks of registers to store operand values, an accumulator comprising a pool of registers to store operand values determined to cause a conflict at register banks within the register file and cache circuitry to control storage of the operand values determined to cause a conflict at the register banks from the register file to the pool of registers.

Accumulator pooling mechanism

An embodiment of a semiconductor package apparatus may include technology to determine one or more conditions for a set of primitives, and perform primitive replication at a vertex shader based on the determined one or more conditions for the set of primitives. Other embodiments are disclosed and claimed.

Vertex shader with primitive replication

Growing community of inventors

Otomin, Poland

Tomasz Bujewski